Next-generation Toshiba 'BiCS FLASH' includes 3-bit/cell (TLC) technology

Toshiba Corporation has unveiled a next-generation BiCS FLASH™ 3D flash memory with a stacked cell structure*.

Sample shipments of the world's first 64-layer stacked product have begun. This new device incorporates 3-bit/cell (TLC) technology and has a capacity of 256 gigabits (32 gigabytes), serving as a demonstration of the potential of Toshiba's proprietary architecture. Toshiba plans to continue improving BiCS FLASH™ and aims to launch a 512-gigabit (64 gigabyte) 64-layer stacked product as its next goal.

This product succeeds the existing 48-layer BiCS FLASH™ and utilizes a state-of-the-art 64-layer stacking process to achieve a 40% increase in capacity per chip area compared to the 48-layer process, while reducing the cost per bit and increasing the memory capacity produced per silicon wafer. The 64-layer BiCS FLASH™ can meet demanding performance specifications and can be used in various applications such as enterprise and consumer SSDs, smartphones, tablets, and memory cards.

Since unveiling the world's first prototype 3D flash memory technology in June 2007, Toshiba has continued to develop the technology. The company is currently dedicated to developing BiCS FLASH™ to meet the demands for increased capacity and reduced size.

Toshiba will produce the new 64-layer BiCS FLASH™ at New Fab 2 of its Yokkaichi Operations plant, which officially opened earlier this month. Mass production of the 64-layer BiCS FLASH™ is scheduled to begin in the first half of 2017.