'A30', 0.30µm process technology suitable for sensing applications and analog readout ICs

ams (Korea Country Representative Jong-Deok Lee) announced “A30,” a high-performance analog ultra-low noise CMOS process technology. The new A30 process provides excellent ultra-low noise performance and achieves 0.9 times optical shrinkage compared to ams’s advanced 0.35µm high-voltage CMOS process family.

A30 technology is characterized by providing optimized performance for isolated 3.3V devices (NMOSI and PMOSI), isolated 3.3V low threshold voltage (Vt) devices (NMOSIL and PMOSIL), isolated high voltage devices with thin gate oxide (NMOSI20T), vertical bipolar transistors (VERTN1 and VERTPH), as well as isolated 3.3V ultra-low voltage transistors (NMOSISLN) that provide flicker noise at a level of 0.46 pA/Hz (1 kHz, Ids=1 µA @ Vds=3 V, 10 x 1.2 µm² conditions).

Compared to the H35 process, the new process technology can reduce flicker noise by at least 4 to 10 times for high drain currents. Thanks to these characteristics, the A30 process is suitable for passive components such as various capacitors (poly, sandwich, and MOS variable capacitance semiconductor diodes (varactors)) and resistors (diffusion, well-based, poly, high-resistance poly, and precision).

The A30 process is ideal for ultra-low noise sensing applications and analog readout ICs requiring noise or high signal-to-noise ratio (SNR) optimized at the input, and enables the development of innovative solutions for consumer electronics, automotive, medical, and Internet of Things (IoT) devices.

The A30 process has been fully validated for manufacturability at ams’s state-of-the-art 200mm fab facility, ensuring very low defect density and high yield. All elements of the 0.30µm process were extracted and verified using 0.35µm devices. Optical reduction (0.9x) was performed in the mask shop using the completed GDSII data, resulting in the production of more dies per wafer thanks to the smaller die sizes.

The A30 process is supported by ams’s HitKit, which is widely known as an industry benchmark process design kit. Based on Cadence®’s Virtuoso® Custom IC technology 6.1.6, this new heat kit enables design teams to significantly reduce the time-to-market for competitive products in analog-intensive mixed-signal fields.

By providing high-accuracy simulation models and extraction and verification run sets for Calibre, Assura, and flexible SKILL-based PCells, the new HeatKit offers a comprehensive design environment and proven paths for semiconductors. The new HeatKit V4.15 for the A30 process is available on ams's foundry-supported servers at http://asic.ams.com/hk415.