Hillsboro, Oregon – November 28, 2011 – Lattice Semiconductor (NASDAQ: LSCC) today redefined the low-cost, low-power mid-range FPGA market by announcing its next-generation LatticeECP4™ FPGA family, which provides 6Gbps SERDES, powerful DSP blocks, and IP-based communication engines in low-cost wire-bond packages for cost- and power-sensitive wireless, wired, video, and computing markets. Because the LatticeECP4 FPGA family is based on the award-winning LatticeECP3™ family, it can maintain industry-leading low-power, low-cost characteristics while delivering premium features to key customers. LatticeECP4 devices are ideal for developing key platforms for a wide range of applications, such as Remote Radio Heads (RRHs), distributed antenna systems, mobile base stations, Ethernet aggregation, switching, routing, industrial networking, video signal processing, video transmission, and data center computing.

High-quality SERDES and hard communication engine
The LatticeECP4 FPGA includes up to 16 CEI-compatible 6Gbps SERDES channels along with embedded Physical Coding Sub-layer (PCS) blocks. Since it is available in both low-cost wire-bonded and high-performance flip-chip packages, customers can employ the LatticeECP4 FPGA for both chip-to-chip and long-range backplane applications. The versatile, configurable SERDES/PCS can be fully integrated with a hard communication engine, enabling the economical construction of complete high-bandwidth subsystems. The communication engine provides up to 10x power and cost savings compared to similar FPGA fabric implementations. The LatticeECP4 communication engine portfolio includes solutions such as PCI Express 2.1, multiple 10 Gigabit Ethernet MACs, 3x Ethernet MACs, as well as Serial Rapid I/O (SRIO) 2.1. The integration of the SERDES/PCS and the communication engine is ideal for completing complex serial protocol-based designs and helps shorten time-to-market while reducing cost, power, and footprint.

Innovative DSP processing performance that reduces the number of multipliers
The LatticeECP4 family provides powerful digital signal processing (DSP) blocks along with 18x18 multipliers, a wide ALU, an adder tree, and a carry chain for cascade functions. The unique Booster Logic means that each LatticeECP4 DSP block is equivalent to four LatticeECP3 DSP blocks, enabling up to four times the signal processing performance compared to previous generation LatticeECP3 devices. The flexible 18x18 multipliers can be split into 9x9 or integrated into 36x36, allowing them to perfectly match customer application requirements. Most importantly, since up to 576 multipliers can be cascaded together, complex filters can be built for wireless RRH, MIMO-based RF antenna solutions, video processing applications, and more.

Increased performance and capacity
The LatticeECP4 FPGA provides up to 50% faster performance than previous generation devices and offers a 1066Mbps DDR3 memory interface and 1.25Gbps LVDS I/O which is also available as a serial Gigabit Ethernet interface. The new LatticeECP4 family also provides 66% more logic resources and 42% more embedded memory, enabling design engineers to build complete system-on-chip solutions on FPGAs.

Sean Riley, Executive Vice President and General Manager of the Business Group at Lattice, stated, “The next-generation LatticeECP4 FPGA family provides our customers with an unprecedented combination of premium features, high performance, low cost, and low power that are essential for cutting-edge yet cost-sensitive applications in wireless, wired, video, and computing. Lattice is a pioneer in delivering advanced innovation through cost-effective devices for our customers. With the LatticeECP4 devices now included in our Lattice Diamond® design software, customers can immediately build board-based low-power platforms to expand their markets.”

Design support for LatticeECP4 FPGA
Lattice provides IP (intellectual property) cores, development boards, and design software for the rapid initiation of design activities and rapid time-to-market. The IP cores include CPRI, OBSAI, Serial RapidIO, XAUI, SGMII/Gigabit Ethernet, PCI Express, SMPTE for serial connections, FIR filters, FFT, Reed-Solomon encoders/decoders, CORDIC, CIC, NCO for DSP functions, as well as various other IPs for memory interfaces and connections.

Lattice diamond design environment that can reduce development time
Customers can now start designing with LatticeECP4 FPGAs using Lattice Diamond 1.4 Beta design software. Lattice Diamond design software is the new flagship design environment for Lattice FPGA products, providing a complete set of powerful tools, efficient design flows, and user interfaces to enable designers to develop low-power, cost-sensitive FPGA applications more rapidly. Furthermore, Lattice Diamond software continues to provide industry-leading features specifically developed for low-cost, low-power applications. These include highly accurate power calculators, pin-based simultaneous switching output noise calculators, and proven MAP and PAR FPGA implementation algorithms, which help ensure low-cost and low-power design solutions.

About the LatticeECP4 FPGA family
The LatticeECP4 FPGA family consists of six devices that provide standard-compliant multi-protocol 6G SERDES in low-cost wire-bond packages, DDR1/2/3 memory interfaces supporting speeds up to 1066 Mbps, and powerful, cascadable DSP blocks ideal for high-performance RF, baseband, and image signal processing. The LatticeECP4 FPGA toggles at 1.25 Gbps and offers high-speed LVDS I/O as well as up to 10.6 Mbits of embedded memory. Logic density varies from 30K LUTs to 250K LUTs, and it provides up to 512 user I/Os. The high-performance features of the LatticeECP4 FPGA family are as follows:

· A DSP block supporting up to 36x36 multiplication and accumulation functions operating at >500MHz. DSP slices also provide innovative cascading capabilities to implement wide ALU and adder-tree functions without performance bottlenecks in FPGA logic. The DSP block provides booster logic to support four times the bandwidth per DSP block compared to previous generation DSP architectures.

· 6Gbps SERDES CEI-6G jitter compatibility and the ability to mix and match multiple protocols on each SERDES quad. This includes PCI Express 2.1, CPRI, OBSAI, XAUI, Serial RapidIO 2.0, SGMII/Gigabit Ethernet, 10 Gigabit Ethernet, etc. The SERDES/PCS block is designed to specifically support low-latency variation CPRI link designs used in wireless base stations supporting RRH connectivity. A hard communication engine block using a hard metal array providing PCI Express 2.1 and RapidIO 2.1 blocks, as well as multiple 10GbE and 3x MAC blocks. These blocks support more than 10 times the space and power efficiency compared to traditional FPGA-based implementations.

· Provides compatibility with the SMPTE Serial Digital Interface standard, along with unprecedented performance capable of independently supporting 3G, HD, and SD video broadcast signals on each SERDES channel. Triple support is performed without any oversampling techniques, so it consumes only the minimum possible power.

· 1.25Gbps LVDS I/O that supports the implementation of SGMII/GbE links and interfaces for high-performance ADC/DACs with a CDR (clock data recovery) block. Since CDR functions can be performed on general-purpose I/O, the number of serial I/Os provided to designers is greatly increased, and even when a large number of SERDES channels are required, a smaller number of FPGAs can be used, which can significantly reduce the cost of implementing serial Ethernet interface logic.

Due to these features, the LatticeECP4 FPGA family is optimized for computing applications as well as for mass-produced cost and power-sensitive wireless infrastructure, wired access equipment, video and imaging.

Supply period
Major customers are already proceeding with designs based on LatticeECP4 FPGAs using Lattice Diamond 1.4 beta design software. Device samples are scheduled to be available in the first half of 2012, and mass production is scheduled for the second half of 2012.