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Xilinx Integrates Flexible Transceiver Technology for Optical and High-Performance Interconnect
Published2017.07.04 11:00Xilinx announced the integration of 56G PAM4 transceiver technology into the Virtex® UltraScale+™ FPGA.
Built on and verified in 16-nanometer FinFET+ FPGA fabric, this device extends the Virtex product line to deliver next-generation Ethernet deployment and enables flexible migration of existing systems to next-generation backplane, optical, and high-performance interconnect.
Using integrated devices targeting wired communication, data center, and wireless backhaul applications, customers can overcome the physical limitations of data transmission at 56G+ line speeds, thereby doubling bandwidth in existing infrastructure.
Ken Chang, Vice President of Xilinx's SerDes Technology Group, stated: "Xilinx is leading transceiver technology by combining 56G PAM4 in 16-nanometer FPGAs. These new devices are built on proven FPGAs and will be utilized in diverse applications alongside optical, ASIC, and backplane solutions that will soon be deployed."
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