February 6, 2012 – Qcept Technologies (President of Korea and Asia Pacific, Hong Wan-chul) today announced that it will participate in the world’s leading nanotechnology conferences in the first quarter of this year to share with the semiconductor industry the impact of non-visual defects (NVD) on device yield and overall profitability. As evidenced by Qcept’s increasing reorder rates and use cases in logic, memory and analog manufacturing applications, more and more semiconductor manufacturers and equipment suppliers are choosing Qcept’s ChemetriQ® NVD inspection solution to address NVD yield challenges.

“NVD detection in semiconductor manufacturing is increasingly critical to not only eliminating a growing number of yield-decreasing factors for advanced IC manufacturers, but also improving and optimizing fabs by reducing chemistry usage, shortening cycles, and increasing equipment throughput and efficiency,” said Robert Newcomb, Vice President of QSEP Technology. “QSEP aims to present the latest progress we have made in working with our customers and partners to help the semiconductor industry understand the benefits of incorporating NVD inspection into their yield management strategies.”

QSEP will be attending the following major conferences during the first quarter of 2012:

SEMICON Korea Metrology and Inspection Forum / February 7, 2012, COEX, Seoul
At the SEMICON Korea Metrology & Inspection Forum, Dr. Sungjin (Jason Cho), Senior Process & Yield Engineer at QSEP Technology, will present on yield-limiting NVD-related inspection solutions for process-induced charging and sub-monolayer organic and metallic residues to enable advanced process control and yield engineering. Dr. Cho’s presentation is scheduled for Session 2, beginning at 4:00 p.m. on February 7.

19th Korean Conference on Semiconductors / February 15-17, 2012, Korea University, Seoul
At the 19th Korea Semiconductor Conference (KCS), Dr. Seong-Jin Cho of QSEP will present an overview of the emerging NVD and examples of NVD inspection utilization for increasing yields in semiconductor fabs. Dr. Cho’s presentation is scheduled for 3:30 p.m. on February 17.

SEMATECH Surface Preparation and Cleaning Conference / March 19-21, 2012, Austin, Texas
At the SematekSPCC conference, QSEP and Samsung Electronics will present a joint paper on the impact of charge NVD that occurs during the After Develop Inspection (ADI) phase and leads to physical pitting defects during the After Clean Inspection (ACI) process. Charge NVD serves as a leading indicator for physical defects in advanced node gate oxide modules and ultimately the yield of affected devices.

*Photo Caption: “High-resolution charge map showing defects using QSEP ChemetriQ equipment”
The large image is a wafer map provided by the Q-SEP equipment, showing the charge (voltage) accumulated in the middle of the wafer during the semiconductor wafer process. The charge is a type of NVD, and charge NVD cannot be detected by optical inspection equipment, but can only be detected by the Q-SEP equipment. The small image in the photo shows where the actual yield loss occurred on the wafer. The same area where the Q-SEP equipment detected the charge accumulation.
It is a part.