March 14, 2012 – The MIPI Alliance announced the Low Latency Interface (LLI) v1.0 specification for mobile devices, providing point-to-point (P2P) interconnects between application processors, modems, and baseband processors. This high-bandwidth interconnect is designed to allow baseband processors to directly access the application processor's dedicated DRAM memory, eliminating the need for separate dedicated DRAM. The industry estimates that this will reduce the Bill of Materials (BoM) by $2 per smartphone. As circuit boards can also be reduced, mobile device manufacturers expect to be able to decrease mounting area. More details can be found at www.mipi.org/LLI .

"The MIPI-LLI specification is a solution that provides outstanding innovation in mobile device system architecture," said Joel Huloux, Chairman of the Board of Directors of the MIPI Committee. "This specification has opened the door to many design options. Our MIPI Committee members will continue to overcome the limitations of interface technology to provide benefits to the entire mobile ecosystem."

Improved data flow with layered TLP (Transaction-Level Protocol)
The MIPI-LLI specification is intended for low-latency cache refill transactions. An initiator (transmitting commands) and a target (receiving commands) on the application processor and baseband processor exchange transactions without software intervention to reduce latency. This specification also defines the best traffic class and is used as a device to connect two semiconductors on the same PCB or to distant memory with two wires without degrading the performance of latency-sensitive traffic. Therefore, the LLI interface improves system-wide communication by enabling sideband signal transmission between two chips.
Interface layers start from the industry-standard physical layer. MIPI-LLI utilizes the wideband MIPI M-PHYSM, a method widely used for interconnecting peripheral chips in many mobile phones and consumer applications.

Extend product life and reduce design time with scalable solutions
By using a common physical layer, the MIPI-LLI specification provides a scalable solution capable of accommodating the requirements of future mobile phones. The design configuration allows for the use of multiple transport modes, enabling mobile device manufacturers to differentiate their products according to customer needs. MIPI-LLI also reduces overall power consumption by utilizing M-PHY SLEEP and HIBERNATE power modes.

SoC designers can connect multiple chips in a daisy-chain fashion to allow them to share a single memory chip. This is an innovative method that enables multiple chips to access a single DRAM simultaneously using just two pins, whereas previously, each semiconductor chip required over 100 pins to individually handle high- or low-capacity DRAM. This design flexibility extends phone battery life, the product lifespan of application and baseband processors, and reduces design time for device manufacturers.

Reduce pin count with standard interfaces and make testing easy
Compared to the existing interchip interface solution known as Chip2Chip, the MIPI-LLI interface significantly reduces the number of pins to a minimum of 2 pins and extends the actual connection distance between chips to nearly 100 cm. As the number of pins in MIPI-LLI increases, M-PHY provides scalability for high-speed devices, enabling applications to achieve high throughput and low latency using fewer pins than C2C, even when using higher-specification devices.

High advantages due to extensive industry support
Since the MIPI-LLI committee began standardization work in 2009 with existing participants including Arteris, Agilent Technologies, Inc., Arasan Chip Systems Inc., Arteris Inc., BitifEye Digital Test Solutions, Broadcom Corporation, Intel Corporation, Motorola Mobility, Inc., Renesas Electronics Corporation, Qualcomm Incorporated, Research In Motion, Samsung Electronics, ST-Ericsson, Synopsys, Inc., Texas Instruments Incorporated (TI), and the University of New Hampshire InterOperability Lab (UNH-IOL) have participated and actively supported the project.

Charlie Janac, President and CEO of Arteris, said, “MIPI LLI provides SoC designers with a software stack-free method to share a single memory between two chips using fewer pins than other solutions. Arteris has contributed to the establishment and implementation of the LLI specification since the beginning and will continue to contribute by participating in the MIPI-LLI division.”

John Koeter, Vice President of IP and Systems Marketing at Synopsys, stated, “The new LLI provides scalable and low-power solutions that help developers reduce costs and space in products developed for high mobility,” adding, “As a long-time member and supporter of MIPI“As such, Synopsys will continue to supply IP that supports the rapid evolution of the mobile market, including LLI-compatible DesignWare® MIPI M-PHY IP solutions that enable highly competitive and future-proof designs with high data rates and low power consumption,” he said.

Brian Carlson, Executive Vice Chairman of the MIPI Committee and TI’s Chief Technology Strategist, stated, “Since identifying the demand for industry-standard Low Latency Interface (LLI), I have served as the head of the division developing LLI specifications and have fully supported the MIPI LLI interface. TI developed the OMAP™ platform as a discrete architecture to ensure design flexibility through the way it connects with modems, OMAP processors, and bridges. TI’s OMAP5 multicore application processors will utilize Arteris’s MIPI-LLI technology to pair with partners’ chips, paving the way for optimal system solutions.”