Certified for TSMC's 5nm and 7nm processes
Improve design confidence by checking PERC constraints.
Mentor, a Siemens business, today announced that its Mentor Calibre nmPlatform and Analog FastSPICE (AFS) Platform have been certified for TSMC's 7nm FinFET Plus and the latest version of its 5nm FinFET process. Mentor also continues to expand the capabilities of its Xpedition Package Designer and Xpedition Substrate Integrator products in support of TSMC's advanced packaging offerings.

“Siemens’ continued strategic investment in electronic design automation (EDA) technologies will position TSMC and Mentor’s joint customers to more successfully bring next-generation IC products to market,” said Suk Lee, senior director of design infrastructure marketing at TSMC.

Mentor has enhanced its Calibre nmDRC and Calibre nmLVS tools for TSMC's 7nm FinFET Plus process and the latest version of its 5nm FinFET process. Furthermore, Mentor continues to provide TSMC's customers with the functionality and performance they need to achieve their manufacturing requirements. Calibre nmDRC and Calibre nmLVS are cloud-ready tools that are being deployed today on customer server solutions comprising thousands of CPUs.

Mentor's Caliber YieldEnhancer tool is certified for TSMC's 5nm and 7nm FinFET Plus processes. The proprietary fill routine developed by Mentor and TSMC achieves manufacturing requirements by precisely controlling the location of fill shapes. The Calibre YieldEnhancer tool's capabilities, combined with TSMC's Calibre Fill Design Kit, maximize insertion rates.

The Calibre PERC reliability platform is certified for TSMC's 5nm and 7nm FinFET Plus processes. Furthermore, the latest version of TSMC's PERC constraint check function allows TSMC customers to enhance the reliability of their designs.

Mentor continues to enhance its toolset to support TSMC’s InFO_MS (Integrated Fan-Out with Memory on Substrate) advanced stacked packaging offering. In addition to its ability to create and manage complex interconnects between components, Mentor’s Xpedition Substrate Integrator, the primary automation tool in Xpedition Package Designer for layout, has been extended to automate the generation of source netlists to enable connectivity checking in Calibre 3DSTACK. Calibre 3DSTACK for layout-to-schematic comparison (LVS), Calibre nmDRC, Calibre xACT for interface coupling capacitance extraction, and Calibre PERC for point-to-point checking are also part of TSMC’s InFO_MS reference flow. These enhancements provide a comprehensive implementation and verification solution for the design flow of TSMC InFO_MS.

The AFS platform, including the AFS Mega circuit simulator, is certified for TSMC's 7nm FinFET Plus process and the latest version of its 5nm FinFET process. Analog, mixed-signal, and RF design teams at leading global semiconductor companies are using the AFS platform to verify their chips designed with TSMC's latest technologies.

“Mentor is proud to partner with TSMC to license our core technologies, enabling our customers to bring IC innovations to market more quickly,” said Joe Sawicki, executive vice president (EVP) of Mentor’s IC division. “Mentor and TSMC will provide our joint customers with more design paths and enable them to rapidly implement IC products for the mobile, high-performance computing, automotive, AI and IoT markets.”