Xilinx Korea (Country Manager Ahn Heung-sik) July 27, 2012 – Xilinx announced the completion of the first free release of its next-generation design environment. Vivido™ Design Suite 2012.2 is available at no additional cost to any ISE® Design Suite customer with a valid warranty. This is the first phase of the release, which will be rolled out in two phases. The first phase focused on accelerating implementation timelines in C and RTL, while the upcoming second phase will focus on accelerating system-level feature integration timelines. Vivado Design Suite 2012.2 provides a highly integrated Design Environment (IDE) with a completely new generation of system-IC tools, including High-Level Synthesis (HLS), RTL integration with industry-leading SystemVerilog support, innovative analytical place and route, and an advanced SDC-based timing engine, enabling developers to increase productivity in design implementation at more than four times the speed.

Vivado Design Suite Accelerates RTL Implementation
Due to the scale and complexity of today's designs, developers are facing multidimensional design problems that are difficult to achieve through automated design completion. The Place and Route technology in Vivado Design Suite 2012.2 accelerates implementation cycles by optimizing multiple concurrent design matrices, such as congestion, total wire length, and timing, through analytical techniques. A 15% performance improvement has been achieved for complex designs. This 15% performance improvement is one level higher than the ISE Design Suite speed rating. In addition, these performance improvements have enabled Xilinx to strengthen its leadership in high performance by being three tiers ahead of competing devices in the mid-range product family, providing better power-to-performance ratio in the high-end product family of the portfolio, and improving performance in the low-end product family.

Luc Burgun, CEO, President, and Founder of EVE, said, “We are pleased that Xilinx has introduced ASIC-class tools to the FPGA industry through the Vivado Design Suite Early Access Program,” adding, “This Vivado Design Suite has significantly increased our productivity with advanced place and route algorithms and a sophisticated design analysis environment, and has enabled us to gain a time-to-market advantage.”

Vivado Design Suite Accelerates C Implementation
With the launch of Vivado High-Level Synthesis (HLS) for All Programmable 7 Series FPGAs and Zynq™-7000 EPP SoC devices, Xilinx continues its leadership in Electronic System Level (ESL) design through the full release of the Vivado Design Suite. Customers of the ISE Design Suite DSP Edition and System Edition currently under warranty can access Vivado HLS at no additional cost. Designers can synthesize C, C++, and System C code into RTL to rapidly validate implementation architectures for complex algorithms. Furthermore, Vivado HLS is being integrated with System Generator tools to create high-speed simulation models, enabling the rapid development of applications such as video, imaging, radar, and baseband radio. Vivado HLS not only accelerates algorithm implementation but also improves system performance by reducing verification time by up to 10,000 times and enabling RTL microarchitecture verification.

Hengqi Liu, CTO of ZTE China’s Central Research & Development Data Center, stated, “We always use C to rapidly build system-level models to verify key algorithms and architectures in FPGA design, but we frequently encounter challenges in quickly and efficiently converting C into a hardware description language.” He added, “Xilinx’s Vivado HLS (High-Level Synthesis) successfully resolved this issue. Recently, after implementing core algorithms using C, we were able to successfully map the C code to Verilog using this tool. Having verified both its functionality and performance on Xilinx devices, it has been found that Vivado HLS is highly useful for the FPGA design workflow.”

Integration and Xilinx Alliance Program
To further enhance designer productivity, Xilinx is collaborating with key Xilinx Alliance program members to validate IP cores and expand the tools of the ISE Design Suite and Vivado Design Suite as design tools. This collaboration is key to Phase 2 of the Vivado Design Suite launch, which includes the interactive design validation environment Vivado IP Integrator and Vivado IP Packager, which enables Xilinx, third-party IP providers, and end users to put cores, modules, and finished designs, along with all constraints, test benches, and resources, into a single package.

Supply timing
Under the warranty, customers of the ISE Design Suite Logic Edition and Embedded Edition will receive the new Vivado Design Suite Edition, and customers of the ISE Design Suite DSP and System Edition will receive the new Vivado Design Suite System Edition at no additional cost.

New features and methodologies to accelerate system integration are scheduled to be released early next year as part of Phase 2 of the Vivado Design Suite launch. The latest versions of the ISE Design Suite and Vivado Design Suite are available for download at Xilinx.com, and customers can sign up for Vivado Design Suite training courses.