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Fabless, Now Available with EDA Tools at 1% of Purchase Cost

Google 우선 소스Published2019.10.22 11:26
Usage fee, 1% or 0.1% of purchase price
Implemented at the end of October, preferential treatment for startups under 3 years old



Expensive EDA tools can now be used at a low cost.
Ministry of Science and ICT supports joint use of EDA tools for domestic fabless companies

On the 21st, the Ministry of Science and ICT allocated a supplementary budget of 4.6 billion won to support joint use of semiconductor automation design software (Electronic Design Automation; EDA) tools for fabless companies.

To provide full-fledged support, an information session was held for domestic fabless companies in Pangyo, Seongnam-si, Gyeonggi-do on the 22nd.

EDA tools are essential tools for fabless companies, but they are expensive, costing 100 to 200 million won per tool, which is a significant burden for small and medium-sized fabless companies and startups. Each fabless company uses about 10 different EDA tools, and about 80% of semiconductor development costs are spent on EDA tools and prototype production.

According to the results of a policy demand survey conducted from May to June targeting 87 domestic fabless companies, 38 companies preferred EDA tool support as their top priority.

The Ministry of Science and ICT conducted a demand survey targeting small and medium-sized fabless and start-up companies, and selected 29 EDA tools with high demand through a committee of experts. It plans to install the EDA tools on servers within the 'HPC Innovation Hub' located in Pangyo and support their use from the end of October.

Fabless companies wishing to use EDA tools can submit an application for use by email to the Pangyo Center of the Electronics and Telecommunications Research Institute, the implementing agency, and pay the usage fee to access the server from their own computers and utilize the EDA tools.

The usage fee is set at approximately 1% of the individual purchase cost, and startups within 3 years of establishment will be given preferential treatment by setting the fee at approximately 0.1% and allowing them to use it first.

Detailed information about this semiconductor EDA tool joint use support project can be found on the Korea Electronics and Telecommunications Research Institute and HPC Innovation websites.
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