October 9, 2012 – Communication infrastructure, video equipment, industrial measurement equipment, military electronic equipment, and other multi-channel data-intensive systems are requiring wider resolutions and higher sampling rates starting from the data conversion stage. In addition, physical layout constraints of parallel interfaces and bit rate limitations of serial LVDS (low-voltage differential signaling) techniques have begun to emerge as technical challenges for designers.

Analog Devices ( www.analog.com , NASDAQ: ADI), a global leader in high-performance signal processing technology and data converters, announced the release of the AD9250, a dual-channel 14-bit 250MSPS A/D converter that adopts the JEDEC JESD204B serial output data interface standard to address these challenges. The AD9250 A/D converter is the industry's first to provide JESD204B Subclass 1 deterministic latency at 250MSPS. Thanks to these features, the AD9250 can precisely synchronize multiple data conversion channels through the serial interface.

• Download data sheet, order samples and evaluation boards: http://www.analog.com/AD9250
• View details on ADI's JESD204 serial interface technology: www.analog.com/JESD204
• Watch the “Understanding JESD204B High-Speed Data Converter vs. FPGA Interface” webcast: http://www.analog.com/en/content/WC_JESD204B/webcast.html

The serial interface implementation of the AD9250 A/D converter provides a data rate of up to 5 Gbps through a 1-lane or 2-lane capable link. It can provide a full 250 MSPS dual A/D converter data rate using two serial lanes, or support a lower sampling rate using one lane.

High-performance FPGA vendors such as Xilinx are adopting on-chip JESD204B SerDes (Serializer/Deserializer) ports in their latest generation products. Such seamless end-to-end connectivity for analog signal chains not only simplifies PCB layouts but also enables rapid prototype development and reduces time-to-market.

Sunil Kar, Senior Director of Xilinx’s Wireless Business Group, stated, “Xilinx has pledged support for the JEDEC JESD204B standard and is striving to accelerate the adoption of serial interconnect technology in data converters. As part of these efforts, we are providing advanced programmable IP with excellent flexibility and scalability to interface with high-speed data converters such as the AD9250. Xilinx supports JEDEC JESD204B IP with Subclass 0, 1, and 2 capabilities and offers devices that support line rates of up to 10.3 Gbps and lane widths of up to eight times. By combining these enhanced technologies, ADI will be able to increase system modularity, reduce costs and complexity, and improve the performance and functionality of next-generation wireless and wired networks.”

Kevin Kattmann, Director of the High-Speed Converter Group Product Line at Analog Devices, stated, “This flagship product from Analog Devices provides an innovative and highly integrated solution when designing analog signal chains for FPGA-based systems. The AD9250 dual 14-bit A/D converter not only delivers unprecedented broadband signal processing performance, but its simplified serial interface also enables the overcoming of design barriers for next-generation FPGA-based applications in software-defined radio (SDR) equipment and medical ultrasound equipment.” “Now, many system designers have access to excellent solutions to address I/O challenges when designing high-performance analog signal chains,” he said.

Additional Benefits of the AD9250 14-bit A/D Converter
The JESD204B serial interface of the AD9250 converter enables the number of required high-speed differential output data paths to be reduced from up to 28 per IC to just 2. The AD9250’s Subclass 1 deterministic latency feature ensures that link resynchronization events are repeated with every power-up cycle. This is a critically required characteristic in fields such as diversity radio systems and instruments, multi-mode digital reception applications (TD-SCDMA, WCDMA, LTE (especially 2R2T > 8R8T evolution), radar/military electronics, medical imaging systems, cable infrastructure, and general-purpose SDR equipment.

Key specifications of the AD9250 14-bit A/D converter
• JESD204B encoded serial digital output, Subclass 1 deterministic delay function
• SNR = 70.6dBFS (at 185MHz AIN and 250MSPS)
• SFDR = 88dBc (at 185MHz AIN and 250MSPS)
• IF Sampling Frequency: Max 400MHz
• 95dB Channel Isolation/Crosstalking
• Low power and small package

Evaluation kit
The combination of the AD9250-250EBZ (250MSPS), AD9250-170EBZ (170MSPS), and AD6673-250EBZ DUT boards with the HSC-ADC-EVALDZ high-speed data acquisition card provides a comprehensive signal performance optimization evaluation system for the AD9250. The acquired data can be analyzed using a notebook PC and Analog Devices' free software called VisualAnalog™. In addition, for compatibility with FPGA development platforms, a CVT-ADC-FMC-INTPZB FMC interposer connector for DUT boards is also provided.

Price, supply, and complementary products
The AD9250 dual-channel 14-bit 250MSPS A/D converter is suitable for use with other Analog Devices products, such as the AD8138, ADA4937, and ADA4938-2 driver products used in baseband differential analog input configurations, or the AD9516-3 clock divider IC which adopts the ADCLK905 low-jitter clock buffer.
In addition, Analog Devices supplies a 170 MSPS pin-compatible product (AD9250-170) and an 11-bit 250 MSPS pin-compatible version, the AD6673.

IGHT: 14.25pt; BORDER-TOP: black 0.5pt solid; BORDER-RIGHT: black 1pt solid" class=xl65 height=19 width=88> Product WIDTH: 74pt; BORDER-TOP: black 0.5pt solid; BORDER-RIGHT: black 0.5pt solid" class=xl67 width=98> Package0 rowSpan=2 width=69> possibleCKGROUND-COLOR: transparent; WIDTH: 66pt; HEIGHT: 27.75pt; BORDER-TOP: black; BORDER-RIGHT: black 1pt solid" class=xl68 height=37 rowSpan=2 width=88>AD9250-170: black 0.5pt solid" class=xl78 width=98> -="BORDER-BOTTOM: black 0.5pt solid; BORDER-LEFT: black; BACKGROUND-COLOR: transparent; WIDTH: 98pt; BORDER-TOP: black; BORDER-RIGHT: black 0.5pt solid" class=xl77 width=130> $300R: transparent; WIDTH: 52pt; BORDER-TOP: black; BORDER-RIGHT: black 0.5pt solid" class=xl77 width=69> -R: transparent; WIDTH: 66pt; HEIGHT: 27pt; BORDER-TOP: black; BORDER-RIGHT: black 1pt solid" class=xl79 height=36 width=88>CVT-ADC-FMC-INTPZB

Sample supply	Mass production supply	price
AD9250-250	possible	$131.57	48-Lead LFCSP
		(Based on 1,000)
possible	possible	$72.50/FONT>	48-Lead LFCSP
		(Based on 1,000)
AD6673-250	possible	possible	$74.80	48-Lead LFCSPPAN>
			(Based on 1,000)
AD9250-250EBZ	-N>	possible	$350	-
f="http://www.analog.com/AD9250" target=_blank> AD9250-170EBZ	-	possible	$300
AD6673-250EBZ	-	possible	-
HSC-ADC-EVALDZ	possible	$750	-
-	possible	$99	-

• Check out ADI solutions for Xilinx FPGAs. http://www.analog.com/en/alliances/xilinx/topic.html
• Visit EngineerZone™, ADI's online technical support community, to check the latest news and information. http://ez.analog.com/community/data_converters/high-speed_adcs