EUV, with a shorter wavelength than ArF, enables semiconductor process refinement.
EUV process requires power source and causes severe metal contamination
Parallel use with DPT/QPT processes below 5nm


Moore's Law states that semiconductor chip performance doubles every 18 months. This law, proposed by Intel co-founder Gordon Moore in 1965, has been the basis for semiconductor companies' manufacturing strategies.

However, since the 2010s, the increasing difficulty of process miniaturization has slowed the improvement in semiconductor chip performance, raising many questions about Moore's Law. However, with the full-scale adoption of extreme ultraviolet (EUV) lithography in semiconductor manufacturing, Moore's Law is expected to be extended.

According to the Korea Semiconductor Industry Association (KSIA), the wavelength of EUV is 13.5 nm, which is much shorter than the 193 nm of argon fluoride (ArF), which has been widely used so far, and can increase the precision of semiconductor exposure processes.

The EUV process, which is attracting attention as a method for realizing next-generation semiconductor microfabrication, is currently being applied mainly in logic and foundry processes. In both fields, it is more cost-effective to use the EUV process than the DPT (Double Patterning Technology)/QPT (Quadruple Patterning Technology) process at 7nm or below.

However, the industry predicts that rather than solely relying on EUV technology to achieve cost competitiveness, EUV technology will likely be responsible for some microfabrication processes. EUV is extremely difficult to implement, requiring separate power plants for power, and is also prone to metal contamination.

Currently, the industry largely relies on existing ArF immersion equipment to implement fine patterns. ArF immersion can theoretically be used up to the 40nm process. For processes below 30nm, the DPT process is used in addition to ArF immersion equipment.

EUV technology enables 7nm and 5nm processes without repeating the exposure process. The challenge lies in mass production. Therefore, technology development is expected to focus on using EUV locally in areas requiring fine patterns, while utilizing conventional immersion processes for other areas.

Furthermore, implementing EUV for processes below 5nm will require the introduction of a DPT process alongside EUV. Therefore, for processes below 5nm, it seems likely that DPT and QPT processes will need to be utilized alongside EUV.

It is expected that future exposure processes will be developed by combining various technologies rather than applying a single technology. Process refinement is expected to continue through EUV technology and the development of alternative technologies, including DPT and QPT, which are existing exposure repetitive processes.

◇ The introduction of EUV will also change semiconductor structures and materials.

In the logic and foundry fields, EUV is being introduced after 7nm, and 3D structure technology development is also progressing in parallel.

Up to the 5nm or 4nm process, EUV will be used exclusively, but below 5nm, DPT or QPT technology will be applied to EUV technology, and the structure is also expected to change to the GAA (Gate-All-Around) method that surpasses FinFET.

In the DRAM field, EUV technology will be introduced in earnest after 1zm, and diversification of material technologies such as hafnium oxide (HfO2) in the cap process is expected.