KAIST Develops 3D Integrated Signal Amplifier Technology
III-V HEMT integration on Si CMOS substrate
100nm process approaches 10nm performance


Communication and quantum signals are analog, which means they can become weaker or more susceptible to noise during transmission, leading to signal distortion. Therefore, high-speed signal amplification is essential for transmitting and receiving signals. These amplification devices require characteristics such as ultra-high speed, high output, low power, and low noise. Furthermore, with the advancement of communication technologies like 5G, the systems that comprise them are becoming increasingly complex, further increasing the importance of highly integrated component manufacturing technology.

The Korea Advanced Institute of Science and Technology (KAIST) announced on the 14th that a research team led by Professor Sang-Hyun Kim of the Department of Electrical and Electronic Engineering has developed a compound semiconductor device technology based on monolithic 3D integration that overcomes the shortcomings of existing communication devices. Monolithic 3D integration is a technology that forms an upper thin film layer after the lower device process and then performs the upper device process to improve the alignment of the upper and lower devices.

There are two common ways to implement communication components.

This is a method of implementing an amplifier element using high-density Si CMOS using silicon (Si), and a method of manufacturing an amplifier element using III-V compound semiconductors and packaging other elements using Si CMOS. III-V compound semiconductors are semiconductors formed by compounds of group III elements and group V elements, and have excellent charge transport properties and optical properties.

However, Si technology faces limitations in its physical properties, making it difficult to improve critical device performance, such as cutoff frequency characteristics, for communication devices. There's also the problem of increased noise due to signal interference, such as substrate coupling noise. III-V technology offers superior device noise characteristics, but its integration and packaging processes with other components are complex. The packaging process can also lead to signal loss issues.

A KAIST research team has developed a process and device structure that maximizes the advantages of both devices by three-dimensionally integrating III-V HEMTs (High-Electron Mobility Transistors), which boast superior analog signal amplification performance, onto a Si CMOS substrate. This method involves stacking the devices in three layers and integrating them on the same substrate. At the same time, the team demonstrated the ability to eliminate noise caused by substrate signal interference.

The research team utilized ultra-low-temperature processes, such as wafer bonding, to integrate the upper III-V devices at temperatures below 300°C, maintaining the performance of the underlying Si CMOS even after the upper device integration. Furthermore, by introducing an InGaAs/InAs/InGaAs quantum well structure to fabricate the upper III-V devices, they realized electron transport characteristics. It was also revealed that superior performance can be achieved without using a sub-10nm process by using a 100nm (nanometer) process.

In addition, it was experimentally demonstrated for the first time that the noise caused by substrate interference in existing SI CMOS can be resolved by fabricating the device in a three-dimensional integrated form.

Professor Kim Sang-hyun said, “This technology can also be applied to quantum qubit decryption circuits,” and added, “We will focus on follow-up research to ensure that it can be utilized in various fields.”

Meanwhile, this study was conducted by KAIST Department of Electrical and Electronic Engineering Ph.D. candidate Jaeyong Jeong, with the first author, in collaboration with a research team led by Dr. Jongmin Kim of the Korea Institute of Nanotechnology and Professor Jaehyung Jang of the Gwangju Institute of Science and Technology. The research was also presented at the 'Symposium on VLSI Technology.'