There is a need to optimize PCB layout to improve EMC (Electromagnetic Compatibility) performance of DC/DC, and a forum has been created to share solutions for this.

On the 7th, e4ds eewebinar held a webinar titled 'EMC Countermeasures for DC/DC Converters Part 2' by ROHM Senior Researcher Song Oh-yong.

In this webinar, ROHM Senior Researcher Song Oh-yong reviewed noise sources and propagation paths, and presented noise countermeasures through PCB layout and noise countermeasures through peripheral components.

The sources of conducted and radiated noise in switching DC/DC converters include fundamental frequency generation, ringing, and input voltage fluctuations. It can also be conducted through the cable connecting the power supply and the DUT, and can be radiated into space or as electromagnetic waves from the DUT and the cable.

In actual circuits, there are parasitic C components in the PCB wiring or components, and since the PCB parasitic impedance cannot be eliminated on the IC side, it is necessary to address it in the PCB layout.

Therefore, optimization of PCB layout is necessary to improve EMC performance of DC/DC.

The PCB layout points of the forced DC/DC converter are as follows: △Input capacitors and diodes should be placed on the same side as the IC terminals or FETs and as close to the IC terminals or FETs as possible; △Inductors should be placed close to the IC terminals or FETs, although not as close as the input capacitors, to at least suppress radiated noise from the switching node.

The copper pattern area of the AC loop should not be set too wide and the output capacitor should be placed close to the inductor.

In particular, since crosstalk increases at high frequencies, short pattern spacing, and under Hi impedance conditions on the receiving side, the patterns should not be arranged in parallel to eliminate the effects of crosstalk. If they are arranged in parallel, countermeasures such as leaving sufficient distance, arranging GND between them, or crossing the patterns at right angles are necessary.

As a countermeasure using peripheral components, the high-frequency impedance can be lowered by adding small-capacity ceramic capacitors in parallel. However, you should be careful because the impedance increases inversely due to anti-resonance depending on the frequency, which worsens EMI.

When using a snubber circuit, there is an effect of improving ringing during rise/fall, but there is a disadvantage in that the snubber circuit itself generates heat and reduces efficiency.

The gate resistor has the effect of improving ringing during rise/fall by making the slope of switching smoother as the gate slope of the FET becomes slower. However, this method has the disadvantage that it cannot be used in the case of a MOSFET-embedded type IC.

The BOOT resistor smoothes the rise of switching by placing the resistor in series with the BOOT capacitor, but does not affect the ringing during the fall, and placing the resistor increases the heat generation of the high-side MOSFER.

Looking at the main Q&A, regarding wiring design to reduce ringing, the answer was that in order to reduce ringing, PCB parasitic capacitance must be reduced, and to do this, the wiring must be thick and short. In addition, vias also generate parasitic capacitance, so care must be taken when designing the PCB, and regarding the parasitic impedance of the wiring, the answer was that if the current flowing in the wire is small, the noise is small and can be ignored.

Regarding the Vin and Vout GND patterns, it is recommended to place them at a distance of about 1 to 2 cm to prevent the GND input noise of VIN and VOU from flowing into the output.

Regarding the number of capacitors, it was mentioned that it is effective to use multiple capacitors, but caution is needed regarding the anti-resonance phenomenon when applying multiple capacitances.

When asked whether high-frequency switching noise can be eliminated from the power IC, it was stated that if excessive EMC is considered when designing, the efficiency and heat generation of the IC may be excessive, so product development is necessary at an appropriate level for the IC.