May 30, 2013 – Silicon Labs (NASDAQ: SLAB, Country Manager In-gyu Kim), a global leader in high-performance analog-intensive mixed-signal ICs, today announced crystal oscillators (XOs) that provide ultra-low jitter reference timing for 10G, 40G, and 100G cloud computing and network equipment. The newly released Si535 and Si536 XOs utilize Silicon Labs’ proven DSPLL® technology to provide superior performance, reliability, and flexibility for core and access switches, SAN (storage area networking) equipment, security routers, enterprise switches/routers, and carrier Ethernet switches and routers in 10/40G data centers.

To meet the surging demand for cloud computing-based services, data center equipment is transitioning to high-speed serial data transmission of 10G or higher. Furthermore, there is a strengthening trend to maximize energy efficiency by integrating switches, storage, and other computing resources into fewer components. This trend has led to the emergence of processors, Ethernet switch ICs, and FPGAs equipped with integrated SerDes (serializer-deserializer) technology that require low jitter timing references. Silicon Labs' Si535/536 oscillators provide the ultra-low jitter and ±20 ppm stability required by state-of-the-art cloud computing and networking infrastructure equipment.

The Si535/536 XO provides excellent jitter performance corresponding to less than 200 femtoseconds (fs) RMS jitter (accumulated from 10 kHz to 1 MHz) at general-purpose Ethernet and optical channel reference frequencies. The Si535/536 oscillator supports LVDS and LVPECL output formats at 2.5V and 3.3V, providing total stability of ±20 ppm and 31.5 ppm, respectively, simplifying interfaces for various processors, switches, PHYs, and FPGAs. When used in conjunction with Silicon Labs' differential clock buffers, the Si533xx, the Si535/536 XO provides low-jitter clock generation and distribution suitable for SoCs requiring multiple high-performance reference clocks.

The Si535/536 oscillators utilize DSPLL, patented by Silicon Labs, to provide low-jitter clocks at high-frequency differential outputs. Unlike conventional XOs that require a different crystal for each output frequency, the Si535/536 XOs use a general-purpose fixed-frequency crystal and employ DSPLL technology to generate any output frequency, offering high stability and reliability. Additionally, the DSPLL clock simplifies the task of generating low-jitter clocks in noisy environments commonly found in data centers and networking systems through superior power noise isolation.

DSPLL technology-based oscillators can be supplied at any output frequency without cutting or tuning third-order overtone (OT) crystals or surface acoustic wave (SAW) components, unlike competitors' low-jitter XOs. Silicon Labs' mixed-signal IC-based approach shortens lead times for custom oscillators through simple factory programming at the time of shipment. Samples of the Si535/536 ship within two weeks, offering the shortest lead times in the high-performance frequency control market.

"Cloud computing switches, routers, and storage devices are moving to faster serial data links that require high-performance timing," said Mike Petrowski, Vice President and Head of Timing Products at Silicon Labs. "By combining high performance with simple device customization and high-efficiency manufacturing processes, we supply standard and custom XOs for all frequencies with short and reliable lead times. This streamlines product design cycles and eliminates supply chain issues."