As Intel continues to pursue Moore's Law, it has presented the foundation for innovation in key packaging, transistors, and quantum physics that are essential for advancing and accelerating computing over the next decade.

On the 13th at the IEEE International Electronics Device Meeting (IEDM) 2021, Intel unveiled details regarding hybrid bonding that could improve interconnect density in packaging by more than 10 times, improve transistor area by 30% to 50%, and introduce new power and memory technology innovations, as well as new concepts in physics that could revolutionize computing.

At IEDM 2021, Intel researchers outlined expectations for more than a tenfold improvement in interconnect density in packaging and solutions for the design, process, and assembly challenges of hybrid bonding interconnects.

At the Intel Accelerated event last July, Intel unveiled Foveros Direct and announced plans to significantly increase interconnect density for 3D stacking by achieving bump pitches of 10 microns or less.

Intel is also requiring the establishment of new industry standards and testing procedures to enable a hybrid bonding chiplet ecosystem, so that the ecosystem can benefit from advanced packaging.

Intel is prepared for the upcoming post-FinFET era based on multi-transistor stacking beyond GAA RibbonFETs, and this stacking method incorporates up to 30–50% of logic to continue the advancement of Moore's Law by fitting more transistors per square millimeter. It aims to improve scaling.

Intel is paving the way to improve Moore's Law to advance into the Angstrom era, which includes preliminary research on how to overcome the limitations of existing silicon channels by creating transistors using new materials with a small amount of atomic thickness. This will enable the integration of millions more transistors per die for the next generation of more powerful computing.

In addition, Intel announced in this presentation that it is introducing the following new features.

It provides efficient power technology with the world's first GaN-based power switch incorporating silicon-based CMOS on a 300mm wafer. This minimizes power loss to the CPU and rapidly supplies power, while simultaneously reducing motherboard components and space.

Intel uses new ferroelectrics in its new next-generation embedded DRAM technology to provide low-latency read and write capabilities. This enables the provision of more memory resources to address the increasing complexity of computing applications, ranging from gaming to AI.

Intel is striving to provide not only significant performance through silicon transistor-based quantum computing but also large-scale, power-efficient computing using novel room-temperature devices. In the future, it will be possible to replace existing metal-oxide-semiconductor field-effect transistors (MOSFETs) through entirely new concepts of physics and the following new capabilities.

Intel implemented the world's first magnetoelectric spin-orbit (MESO) logic device at room temperature at IDEM 2021. This result demonstrates the possibility of manufacturing a new type of transistor by changing nano-sized magnets.

Intel and IMEC Labs are conducting research on spintronic materials to carry out device integration research that brings them closer to realizing fully functional spin-torque devices.

Intel demonstrated a 300mm qubit process flow to realize scalable quantum computing compatible with CMOS transistors and presented the future direction of research in the field.