Xilinx, Inc. (NASDAQ: XLNX) today announced the release of the Vivado® Design Suite 2013.3, which supports the new UltraFast™ design methodology and delivers enhanced configuration, plug-and-play IP integration and verification, and partial reconfiguration capabilities. The Vivado® Design Suite is co-optimized with Xilinx’s All Programmable devices and is the programmable industry’s only competitive SoC (System-on-Chip)-based design suite that addresses productivity bottlenecks that can occur in system-level integration and implementation.

Automatic support for new UltraFast design techniques

For fast, predictable design times, Vivado Design Suite 2013.3 provides built-in automation of key elements of the UltraFast design methodology, supports engineers throughout the design cycle with design rule checks (DRC), and provides HDL and constraints templates for optimal design results.

Enhanced configuration, integration, and validation of plug-and-play IP

Xilinx’s Plug-and-Play IP initiative, introduced in 2012, accelerates IP integration by leveraging industry standards such as IP-XACT, IEEE P1735 encryption, and the AMBA® AXI4 interconnect protocol. Earlier this year, the Vivado Design Suite introduced the industry’s first plug-and-play IP integration design environment through IP Integrator (IPI), solving the RTL design productivity bottleneck.

Vivado Design Suite 2013.3 significantly improves usability with enhanced IP integration capabilities and provides over 230 LogiCORE™ and SmartCORE™ IP cores. These enhancements enable a wide range of system implementations through mutual optimization between user designs and Xilinx IP. For example, designers can share clocking resources across the design using connectivity IP such as an Ethernet MAC or PCIe®. Another upgraded feature of this IP is the ability to easily access the transceiver debug port within the IP from the top level. New features in Vivado Logic Analyzer enable designers to fully read/write the AXI system at runtime. In addition, advanced trigger capabilities can be used to perform hardware debug to detect and capture complex events.

Furthermore, Vivado 2013.3 facilitates IP integration through a revision control system and is automated with the verification flow for Cadence's Incisive Enterprise simulator and Synopsys' VCS simulator.

Partial Reconfiguration

Vivado Design Suite 2013.3 supports Partial Reconfiguration, a design technique that has been successfully used by many customers in the ISE Design Suite. This technology maximizes device resource usage by swapping out functions as needed, while also reducing power consumption and enabling field updates without system downtime.

“Vivado’s partial reconfiguration capability for Xilinx’s 7 series devices has contributed significantly to Trendium’s success in delivering a SoC architecture while still meeting PCI Express® requirements,” said Stephen Frey, firmware engineering manager, Trendium, Inc. “Partial reconfiguration allowed us to more efficiently utilize Xilinx’s devices by swapping out protocol analysis modules in our Network Access Agent platform without disrupting the PCI Express link. This approach also allows us to upgrade the existing hardware with new modules for future product enhancements.”

Supply period
Vivado Design Suite 2013.3 is available for download now at www.xilinx.com/download . Register for Xilinx's online training to view Vivado Design Suite training videos and accelerate your productivity by leveraging UltraFast design techniques and Vivado Design Suite-based Targeted Reference Designs.