HONG KONG, November 6, 2013 – Altera Corporation (NASDAQ: ALTR) today announced the release of Quartus® II software version 13.1, further extending its industry leadership in software productivity. The new release delivers powerful algorithmic optimizations and increased parallelism to reduce compile times by an average of 30 percent and up to 70 percent over the previous release. The software also includes the new Rapid Recompile feature, which enables customers to make small source code changes to their Altera Stratix® V FPGA designs. Rapid Recompile eliminates the need for upfront design partitioning by reusing previous compilation results while maintaining performance, saving an additional 50 percent in compile times.

“Altera’s Quartus II software has been able to evolve with each successive generation of FPGA products because of its superior software architecture that has been designed-in and performance-proven from the ground up,” said Alex Grbic, director of software and IP product marketing at Altera. “The latest version of our Quartus II software adds new features and enhancements that deliver a competitive advantage of twice the compile time advantage and 20 percent performance improvement on Altera’s high-end FPGAs.”

This latest release extends the leading edge of Quartus II software by delivering enhancements to high-level design tools, enabling customers to maximize productivity and benefit from the advanced capabilities offered by Altera devices. Quartus II software version 13.1 delivers enhancements to Qsys system integration tools, the DSP Builder model-based design environment, and the Altera SDK for OpenCL™.

* The Altera Qsys system integration tool significantly reduces time and effort throughout the FPGA design cycle by automatically linking together intellectual property (IP) functions and subsystems. Qsys enables designers to rapidly develop systems by seamlessly integrating a variety of industry-standard interfaces, including Avalon, ARM® AMBA AXI, APB, and AHB interfaces. In Quartus II software version 13.1, Qsys further increases productivity with enhanced system visualization that simultaneously displays multiple views of a Qsys system. This makes it much easier to modify the system by adding components or connecting new peripherals.

* The Altera SDK for OpenCL is the industry’s only FPGA OpenCL solution that is currently in production and has passed conformance certification testing to the OpenCL specification defined by the Khronos Group. It provides a software-friendly programming environment for designing high-performance systems using FPGAs on Altera’s Preferred Board Partner Program boards or Altera SoCs when using the Altera Cyclone® V SoC development board.

* The Altera DSP Builder design tool enables system developers to efficiently implement high-performance, fixed- and floating-point algorithms into their digital signal processing (DSP) designs. To provide engineers with more options and flexibility during the design phase, the Altera DSP Builder Advanced Blockset system can now be integrated within MathWorks HDL Coder. Enhancements implemented in fast Fourier transform (FFT) processing include variable FFT size on the fly and super-sampling FFTs for extremely high data rates of 10 GHz, providing unprecedented performance and flexibility options for implementing this common DSP function.

Quartus II software version 13.1 includes best-in-class IP from Altera that delivers up to 70 percent lower latency and more than 50 percent reduced resource utilization while maintaining the performance and throughput of the most popular, highest-performance IP. These IP cores include 10G, 40G, 100G Ethernet, and 25G to 150G Interlaken.

For more information about the features available in Quartus II software version 13.1, visit the Quartus II Software What's New page on the Altera website.