As semiconductor technology continues to develop, competition to improve performance is becoming fiercer. In order to densely integrate transistors on a limited area silicon substrate, the recent trend of process miniaturization has reached 3 nanometers. Experts unanimously say that as the miniaturization process deepens, miniaturization in the next-generation process is reaching its limit.

As diversified approaches to overcome limitations are observed across the semiconductor academia and industry, ideas for new transistor structures, such as 3D stacking technology, are emerging as next-generation technologies.

The era of 32nm Planar FET, which developed miniaturization technology by focusing on leakage current issues through high-K metal gate optimization 20 years ago, has progressed through successive generations through the current mainstream FinFET process starting from 14nm.

Last June, Samsung Electronics succeeded in developing the world's first semiconductor using 3nm GAA (Gate All Around) technology. Starting with 3nm, the era of MBC (Multi-Bridge Channel) FETs based on the GAA process began. The channel changed to a multi-bridge channel structure and became a thin and wide nanosheet shape. This made it possible to easily and diversely control the channel size by adjusting the nanosheet width. It is evaluated that the performance efficiency has been improved as the current can be controlled more finely compared to the existing FinFET process.

The semiconductor process, which is one step more advanced than the existing Fin FET process, has been continuously developing while looking toward the next stage.

The industry says that it takes 20 years from concept idea to commercialization in the semiconductor development process. The industry is already in the stage of anticipating and preparing for the next-generation semiconductor process. For the 2nm process and below, concepts such as vertical FET (VFET) and NC (Nagative Capacitance) FET are being proposed.

Park Jeong-won, a professor of electrical engineering at the University of Nevada, predicted at the ‘Global New Industry New Technology Seminar’ that “when semiconductor technology advances below 2 nanometers, vertical FETs, 2D new materials, and NCFETs will emerge as the next generation.”

In particular, the dominant view is that the transistor structure will move toward a 3D stacking form. 3D stacking, which is limited to NAND flash, is expected to be applied to logic and memory to increase integration after 10 years. Experts predict that Lateral GAA will evolve into Vertical GAA and even 3D VLSI will emerge around 2034.

Professor Park said, “We are researching and developing a nanowire GAA-based negative capacitance GaAs/InN tunnel FET that integrates the ideas of GAA, tunnel FET, and compound semiconductors.” In response to our magazine’s question about the possibility of expanding the application of compound semiconductors to next-generation semiconductors, Professor Park said, “GaN materials can be applied as tunneling transistors,” but “the problem of large-area scaling remains a major challenge.”