Intel has continued innovation to sustain Moore's Law, such as setting a goal of 10 times the integration density in packaging technology and proposing the use of new ultra-thin materials three atoms thick for transistor integration.

Intel announced major research achievements to sustain Moore's Law, including packing one trillion transistors into a single package by 2030, at the International Electronics Device Manufacturers Meeting (IEDM) 2022 on the 5th.

Intel announced 3D packaging technology that will contribute to achieving 10x integration density, a new ultra-thin material three atoms thick for 2D transistors that surpass RibbonFETs, achievements in energy efficiency and memory for higher performance computing, and examples of improvements in quantum computing.

Gary Patton, Executive Vice President of Intel’s Component Research and Design Support, stated, “75 years after the invention of the transistor, the innovation driving Moore’s Law is what continues to address the world’s exponentially growing demand for computing,” adding, “At IEDM 2022, Intel presented forward-looking and specific research results necessary to break through current and future barriers, meet endless demand, and sustain Moore’s Law.” said.

Dr. Ann Kelleher, Intel’s General Manager of Technology Development and Senior Vice President, delivered a keynote speech at the IEDM General Assembly to commemorate the 75th anniversary of the invention of the transistor.

Dr. Keller presented a path for the semiconductor industry to expand the ecosystem around system-based strategies, address increasing computing demand, and innovate more effectively and sustainably at the speed of Moore's Law.

As the global surge in data consumption and advancements in artificial intelligence technology have resulted in the highest computing demand in history, Moore's Law is an essential element in meeting this demand.

Continuous innovation is the cornerstone of Moore's Law. For the past 20 years, the Intel Components Research Group has led innovations to continuously improve power, performance, and cost in personal computers, graphics processors, and data centers, including strained silicon, high-k metal gates, and FinFETs. Currently, the Intel Components Research Group is developing innovative packaging technologies such as RibbonFETs utilizing Gate-All-Around (GAA) transistors, PowerVia (backward power delivery technology), EMIB, and Foveros Direct.

Intel's component research group announced that at IEDM 2022 this year, to continue Moore's Law, it will achieve innovation in three areas: new 3D hybrid bonding packaging technology to seamlessly integrate chiplets, ultra-thin 2D materials to integrate more transistors on a single chip, and energy efficiency and memory for higher computing performance.