Hong Kong, January 28, 2014 – Altera (Nasdaq: ALTR) announced the addition of the JNEye link analysis tool to its suite of verification and board-level design tools. JNEye enables design designers to quickly and conveniently evaluate the high-speed serial link performance of Altera FPGAs and SoCs. The tool offers a new hybrid behavior simulation paradigm by combining the speed of statistical link simulators with the accuracy of time-domain waveform-based simulators. Optimized to support Altera's 10th-generation product portfolio, the JNEye tool provides a platform for evaluating the transceiver link performance of Altera's next-generation FPGAs and SoCs.

Dr. Mike Peng Li, a Fellow at Altera, stated, “We provide a comprehensive range of system-level design tools to enable customers to rapidly simulate and verify how Altera FPGAs and SoCs will operate within their systems. The JNEye link analysis tool is the newest addition to these solutions. By using JNEye, designers can quickly grasp transceiver performance at the board level and accurately understand how Altera devices will interact with other devices within customer systems.”

JNEye tools provide a hybrid modeling technique that combines device characterization models to accurately reflect process/voltage/temperature (PVT) variability. These tools simplify serial link transceiver evaluation by providing realistic simulation accuracy that cannot be achieved using other industry-standard models. Since JNEye supports link simulation using IBIS-AMI device models, it is possible to evaluate serial links between Altera FPGAs and other transmitters or receivers. By using the JNEye link analysis tool, designers can quickly optimize transmit and receive equalization factors for the target bit error rate. This tool can also be used as a post-design support tool to assist with debugging and verification.

JNEye tools are provided as part of a verification and board-level design tool suite within Altera's Quartus II software environment. These tools can analyze systems under real-world conditions, interpret data, and monitor system performance. JNEye tools currently support 28nm Stratix V and Arria V FPGAs, as well as 20nm Arria 10 FPGAs and SoCs. By using these tools, design designers can rapidly verify their board system designs using Arria 10 devices.