TI Unveils Smallest HD DLP® Pico™ Chipset Offering Highest Efficiency
Published2014.02.25 12:43
TI Korea (CEO Kent Chon, www.ti.com/ww/kr ) February 25, 2014 – TI (CEO Kent Chon) unveiled the 0.3-inch HD TRP (Tilt & Roll Pixel) DLP® Pico™ chipset at Mobile World Congress (MWC) 2014. The unveiled chipset features a micro-mirror array with HD resolution that offers the smallest size and highest power efficiency, enabling High Definition (HD) displays in small electronic devices including tablets, smartphones, accessories, wearable displays, augmented reality displays, interactive surface computing, digital signage, and control panels. Based on proven DLP Cinema® technology, the new DLP Pico chip delivers bright, sharp, high-quality HD video. (For information regarding visiting the TI booth at MWC 2014, meeting with DLP Pico experts, and viewing various product demos, please contact dlpmwc@list.ti.com )
The new 0.3” HD TRP chipset utilizes TI’s proprietary Tilt & Roll Pixel (TRP) DLP architecture and the adaptive IntelliBright™ algorithm suite to increase brightness and reduce power consumption compared to the existing DLP Pico architecture. Additionally, with switching speeds reaching up to several thousand times per second, it enables the smallest true-color RGB engine with 120Hz video performance.
To accelerate the development of finished products, TI is actively collaborating with leading developers and manufacturers to launch products utilizing the 0.3” HD TRP chipset in 2014 while maintaining the industry's most extensive Pico ecosystem. More detailed information can be obtained by contacting members of the DLP ecosystem, which includes leading optical engine manufacturers such as Asia Optical, Sekonix, Shenzhen Anhua Optoelectronics Technology, Co. LTD, UneedElectro Inc., and Yong Optics.
"We are already adopting the innovative 0.3” HD TRP chip in Avegant Glyph, a virtual retina display product that projects images directly onto the retina. We selected this chipset based on HD video quality, flexibility, and power savings," said Edward Tang, CEO of Avegant.
"This HD chipset is a significant milestone for DLP," said Frank Moizio, Manager of TI's DLP Pico business unit. "TI can achieve double the pixels on a 0.3-inch MEMS device compared to existing architectures on a frame-by-frame basis, along with 30% higher optical efficiency and up to 50% power savings." He added, "Developers can develop a wide variety of applications and products in smaller form factors."
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