Xilinx Korea (Branch Manager Ahn Hung-sik) February 26, 2014 – Xilinx unveiled the Ultrascale™ MP (Multi-Processing) architecture for the next-generation Zynq® Ultrascale MPSoC at the Embedded World conference being held in Nuremberg, Germany. Building on the success of the Zynq-7000 All-Programmable SoC, the new Ultrascale MPSoC architecture extends Xilinx's ASIC-class Ultrascale FPGA and 3D IC architecture to enable heterogeneous multi-processing as "the right engine for the right task." Xilinx introduced the Zynq-7000 to develop the industry's first All-Programmable SoC, and through the Ultrascale MPSoC has developed the first All-Programmable MPSoC.

The new All-Programmable MPSoC architecture enables processor scalability from 32-bit to 64-bit and provides technical enhancements including visualization support, real-time control and graphics/video processing, combinations of soft and hard engines suited for waveform and packet processing, next-generation coherent interconnect and memory, advanced power management, multiple security, safety and reliability features. The Ultrascale MPSoC architecture combines heterogeneous multi-processing with high-speed FinFET proven in TSMC 16-nanometer FinFET process to improve system performance and integrity at low system power states.

These new architecture elements are combined with the Vivado® Design Suite and automated design environment to significantly reduce programming complexity and increase productivity. This includes C, C++, and OpenCL-based design abstractions, third-party system-level abstractions from Mathworks and National Instruments, IP-based design abstractions and automation. This environment enables easy software migration from the existing standard 28-nanometer Zynq-7000 All-Programmable SoC. The new MPSoC architecture is supported by an extended ecosystem including software, middleware, OS support, debuggers, IP tools, boards, and design services for Zynq devices.