TI Korea (CEO Kent Chon, www.ti.com/ww/kr ) March 14, 2014 – TI (CEO Kent Chon) has released two 4-output and 8-output high-speed current steering logic (HCSL) clock fan-out buffers supporting PCIe (PCI Express) 1.0, 2.0, and 3.0 interfaces. The LMK00334 generates four buffered copies of the input clock, while the LMK00338 generates eight buffered copies. These devices offer 70% lower additive jitter compared to competing devices and eliminate significantly higher supply power noise, providing system designers with sufficient jitter margin for PCIe 3.0 specifications.

Both devices are supported by the WEBENCH® clock architecture and help simplify clock tree design for high-speed communications, networking, and data center systems, including switches and routers. (For detailed information, samples, and ordering the Evaluation Module (EVM), please refer to http://www.ti.com/lmk00338-pr-kr )

It allows for more flexible timing budget allocation across the entire link with 30fs at 100MHz (PCIe 3.0) and 86fs from 1MHz to 20MHz (156.25MHz HCSL), and provides superior noise immunity and jitter performance compared to competing devices with a high power supply rejection ratio (PSRR) of -75dBc at 100MHz. Additionally, two general-purpose inputs operate up to 400MHz and offer the flexibility to be compatible with all input types, including CML, LVPECL, LVDS, SSTL, HSTL, HCSL, or single-ended clocks and crystal oscillators, while pin mode control allows system designers to easily turn individual output banks on and off.

The LMK00334 and LMK00338 can be combined with PCIe clock generators such as the CDCM9102 and CDCM6208 to provide high-performance clock tree solutions. TI's clock dividers and fan-out buffers provide clock tree designers with the flexibility, performance, and enhanced capabilities required to implement a wide range of communications, networking, industrial, and consumer applications.

Engineers can rapidly complete clock tree designs with LMK00334 and LMK00338 using TI’s WEBENCH® Clock Architect. As the industry’s first timing design tool, it can recommend and simulate system clock tree solutions from an extensive device database. It includes features to design phase-locked loop (PLL) filters and simulate phase noise of output clocks. In addition, it provides the ability to fully simulate end-to-end jitter performance for a complete clock tree.

Both LMK00334 and LMK00338 can be verified for functionality and performance specifications using the LMK00338 Evaluation Module (EVM). LMK00334 and LMK00338 IBIS models for simulation are also available.

In addition to this, you can search for relevant solutions in the Clock and Timer forums of the TI E2E™ community and resolve issues through knowledge sharing and Q&A with fellow engineers and TI experts.