3D stacked CMOS transistors using ‘rear power supply technology’ and ‘rear direct contact’ have appeared.

On the 11th, Intel announced that it had presented the next-generation transistor expansion technology and research and development (R&D) results that will support Intel's future semiconductor process roadmap at the 2023 International Electron Devices Meeting (IEDM).

Intel researchers have unveiled progress in 3D stacked complementary metal oxide semiconductor (CMOS) technology using rear-side power supply technology and rear-side direct contact technology.

Additionally, the company announced back-contact technology that extends recent R&D for back-side power delivery, and demonstrated for the first time the ability to integrate silicon and gallium nitride (GaN) transistors in a large-scale 3D monolithic manner on the same 300mm wafer rather than packaging them.

Transistor scaling and back-end power supply technologies are key to meeting the exponentially increasing demands for powerful computing with higher performance.

Intel said, “As Intel enters the Angstrom era and pursues process technology beyond ‘achieving 5 nodes in 4 years,’ the progress of research and development is significant.“This announcement demonstrates our cutting-edge technology development capabilities that can scale the transistors needed for next-generation laptop computing,” said Sanjay Natarajan, senior vice president and general manager of Intel’s Components Research Group.

Intel's Component Research Group continues to advance its engineering innovations through transistor stacking technology and improved back-end power delivery to expand power delivery to more transistors and improve performance, and has demonstrated the ability to integrate transistors made of different materials on a single wafer.

We continue to upgrade our engineering innovations through transistor stacking technology and improved back-end power delivery technology to expand power to a larger number of transistors and improve performance, and we have demonstrated the ability to integrate transistors made of different materials on a single wafer.

Intel's Component Research Group has released its process technology roadmap, focusing on Intel's future: PowerVia rear-side power supply technology, glass substrates for advanced packaging, and Foveros Direct, and expects these processes to enter mass production within 10 years.

Intel is also said to be improving its rear-side power delivery technology, introducing new 2D channel materials, and aiming to pack 1 trillion transistors into a single package by 2030.

Intel has unveiled a revolutionary '3D stacked CMOS transistor' that combines rear-side power delivery technology and rear-side direct contact technology for the first time in the industry.

The latest transistor-related research results announced by Intel are the industry's first vertically stacked complementary field-effect transistors (CFETs) with a gate pitch reduced to 60 nm, catching both area and performance at the same time. A strategy was adopted.

In addition to the stacked CFET, it combines rear power supply technology and rear direct contact technology, which is interpreted as emphasizing Intel's leadership in gate-all-around (GAA) transistors.

Beyond its "five nodes over four years" roadmap, Intel has revealed key R&D areas needed to continue scaling transistors with technologies that deliver power from the back of the transistor.

Intel PowerVia is expected to enter mass production in October 2024, and announced methods to expand and scale rear-side power delivery beyond PowerVia, as well as the advanced core process technologies required to achieve this. Furthermore, the company emphasized the need for rear-side contact and new vertical interconnect technologies to stack transistors in a space-efficient manner.

Meanwhile, Intel also introduced a 300mm wafer that integrates silicon and gallium nitride (GaN) transistors. Unveiling Intel's 300mm GaN-on-silicon wafer, the company demonstrated "DrGaN," a high-performance, large-scale direct circuit solution.