Cadence's timing solutions successfully completed the design of Samsung Foundry's 5G networking SoC.

Cadence Design Systems, Inc. announced on the 12th that Samsung Foundry has successfully achieved tape-out (the stage where the design is completed and transferred to the process) of a 5G networking SoC based on Samsung's 5LPE technology using the 'Cadence Quantus Extraction Solution' and 'Tempus Timing Solution'.

Cadence's Quantus Extraction solution and Tempus Timing solution are solutions used for final verification after chip design. Samsung Electronics Foundry Business Division stated, "By applying Cadence signoff solutions for the first time, we have successfully completed the design with a twofold increase in productivity," and "By utilizing Cadence's integrated flow, we have achieved significant PPA improvements even in a 120M instance design." PPA stands for Power, Performance, and Area.

Additionally, Samsung Electronics Foundry Division shortened the project schedule by quickly achieving design convergence and design closure using the Tempus ECO option within the Cadence Innovus implementation system.

To improve productivity, Samsung Foundry has implemented Tempus' Hierarchical Static Timing Analysis (HSTA) capability to optimize resource allocation and reduce machine and memory demands, while terminating hierarchical designs. Finally, Samsung Foundry leverages Cadence Quantus and Tempus distributed technologies to reduce overall runtimes for complex SoC tasks.

“The successful tapeout of the SF5A design for 5G networking was a significant milestone for our business unit, and the efficiency gains and runtime reductions achieved with Cadence Quantus Extraction and Tempus Timing solutions demonstrate the power of innovation and collaboration between Cadence and Samsung,” said Sangyoon Kim, vice president of Design Technology at Samsung Electronics’ Foundry Business. “We will continue to push the boundaries and leverage the efficiencies of these signoff tools to proactively bring designs to market, and we look forward to building on this success as we continue to advance our projects in the future.”

“Our integrated Quantus Extraction and Tempus Signoff solutions have been instrumental in helping Samsung Foundries achieve increased productivity, improved PPA and time-to-market efficiency,” said Vivek Mishra, vice president, Signoff Group, Cadence Digital. “Samsung Foundries’ ability to achieve its target design metrics while reducing time-to-market is a key achievement from this collaboration, and we look forward to continued collaboration to drive innovation.”

Quantus Extraction and Tempus Timing solutions provide a fast path to tapeout as part of a comprehensive Cadence Digital Full Flow. These tools and flows support Cadence's Intelligent System Design strategy, enabling customers to achieve SoC design excellence.