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Altera Achieves Industry's Fastest Compile Time with Quartus II Software Version 14.0

Google 우선 소스Published2014.07.01 12:12
Hong Kong, July 1, 2014 – Altera (NASDAQ: ALTR) announced that it is providing Quartus® II software version 14.0 as the number one FPGA industry software in terms of performance and productivity. Through this latest version, Altera has reconfirmed its leadership in software for FPGA and SoC design by achieving compile times that are on average twice as fast compared to the closest competing design tool suite.
Quartus II software version 14.0 further enhances user productivity and enables the industry's fastest FPGA and SoC design closure. This latest version offers rapid recompilation capability that can reduce compile time by up to 4x for minor design changes, as well as best-in-class PCI Express (PCIe) IP solutions that deliver enterprise-class performance. Additionally, this latest version expands AXI™ support through the Qsys system integration tool and includes rapid prototyping design flow with Altera SDK for OpenCL.

The newly revised rapid recompilation capability allows users to make minor changes to their design and recompile in a fraction of the time it takes to perform a full compilation. By utilizing the rapid recompilation capability, designers can experience speedups of up to 3x for pre-synthesis HDL changes and up to 4x for post-fitting SignalTap® II logic analyzer changes while preserving placement and routing for unchanged portions of the design. Rapid recompilation currently supports all 28nm Cyclone® V, Arria® V, and Stratix® V FPGAs.

Additionally, Altera continues to provide the best IP portfolio by adding the industry's highest-performing PCIe solution. Altera's best-in-class PCIe solution delivers throughput reaching up to 6.7GB/s and over 400K IOPS (input/output operations per second), improving application performance. This PCIe solution includes a newly designed DMA engine, enterprise-class device drivers, and reference designs, enabling significant simplification of evaluation and design integration work.

Enhancement of the Qsys system integration tool simplifies the task of connecting system-level hardware components. Qsys expands support for AMBA® AXI™3 and AXI4 specifications to include AXI4-Lite, the lightweight version of AXI4, and AXI4-Stream for point-to-point connectivity. These enhancements support a wider variety of custom IP types, facilitate integration with IP developed by Altera and third-party vendors, and enable superior design reuse.

Altera also announced that it is providing Altera SDK for OpenCL version 14.0 for software programmers working with FPGAs. This latest version includes a rapid prototyping design flow that enables programmers to create prototype designs based on FPGA accelerator boards within minutes. This latest OpenCL version also includes multiple reference platforms to further accelerate FPGA development work.
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