Hong Kong - August 5, 2014 - Altera Corporation (Nasdaq: ALTR) announced initial access design software for Stratix® 10 FPGA and SoC, the industry's first design software applied to a 14nm FPGA, building on the success of early customer benchmarking results announced earlier this year. Customers can begin Stratix 10 FPGA designs today and directly experience the 2x core performance gains implemented with the Stratix 10 HyperFlex architecture and Intel's 14nm Tri-Gate process. Altera is providing the Hyper-Aware design flow with innovative Fast Forward Compilation functionality alongside this design software, enabling customers to verify fast design performance and achieve a new level of performance.

Through the dramatically improved core performance of Stratix 10 FPGA and leveraging the innovative capabilities of the HyperFlex architecture that achieves a new level of performance unattainable with previous-generation FPGA architectures, users can now expand the horizons of performance in their designs. Fast Forward Compilation, developed to implement 2x performance improvements in customer designs, identifies performance bottlenecks and provides detailed step-by-step performance optimization recommendations that users can easily implement. Users can also receive estimates of the maximum achievable operating frequency (Fmax) by applying the recommendations provided by Fast Forward Compilation to their designs. With this innovative design flow, Fast Forward Compilation provides customers the opportunity to maximize the full design performance possible in Stratix 10 FPGA and achieve fast timing closure.

Jordon Inkeles, High-End FPGA Marketing Director at Altera, said, "The Stratix 10 design tools we are providing today offer customers the fastest path to market for next-generation FPGAs and SoCs with industry-leading performance," and added "Stratix 10 HyperFlex architecture and Fast Forward Compilation enable customers to double their performance while reducing engineering development time from weeks to months."

Previously, to achieve high performance targets, users had to perform multiple time-consuming design iterations, including various design optimizations and re-running full FPGA compilations to observe the effects of design changes. With Fast Forward Compilation, users receive detailed guidance for design optimization along with the estimated maximum design operating frequency (Fmax) utilizing the HyperFlex architecture. With this insight, customers can estimate achievable performance and make clearer decisions about where to most effectively invest development time to increase design performance and throughput. As a result, Stratix 10 FPGA customers can achieve performance targets with fewer design iteration cycles, simplify the path, and achieve 2x core performance gains.

Stratix 10 FPGA and SoC are designed to implement cutting-edge, highest-performance applications in communications, defense, broadcast, computing, and storage markets while significantly reducing system power. Based on the HyperFlex architecture and Intel's 14nm Tri-Gate process, Stratix 10 FPGA and SoC deliver an average of 2x core performance compared to previous-generation high-performance programmable devices. The HyperFlex, the next-generation core fabric architecture for Altera's Stratix 10 devices, represents the most outstanding structural innovation advancement achieved in the FPGA industry over the past decade and enables applications that cannot be realized with existing FPGA architectures. For high-performance systems with strict power budgets, Stratix 10 devices can reduce power consumption by up to 70% compared to Stratix V FPGA. Stratix 10 FPGA and SoC also provide industry-leading system integration, including the following.