San Jose, California, August 18, 2014 - Altera Corporation (Nasdaq: ALTR) today announced Quartus® II software Arria® 10 Edition v14.0, the industry's most advanced 20nm FPGA and SoC design environment. Altera's performance-verified Quartus II software delivers the industry's fastest compile times and achieves the highest performance for 20nm FPGA and SoC designs. Customers can further shorten Arria 10 FPGA and SoC design cycles by leveraging the extensive portfolio of 20nm-optimized IP cores included in this latest software release.

Altera's 20nm design tools are equipped with industry-leading algorithms and deliver the best results. Quartus II software Arria 10 Edition v14.0 provides compile times that are on average 2x faster than the 20nm design software of the nearest competing product. This productivity advantage enables customers to reduce design iterations and achieve timing closure in 20nm designs rapidly. The software also enables the achievement of highest performance 20nm designs, providing performance advantages beyond speed compared to competing FPGAs.

This latest software release includes a complete set of 20nm-optimized IP cores that further reduce design cycles. The IP portfolio includes standard protocols and memory interfaces, DSP and SoC IP cores. Altera has also optimized key best-in-class IP cores for Arria 10 FPGA and SoC, including 100G Ethernet, 300G Interlaken, Interlaken Look-Aside, and PCI Express Gen3 IP. These best-in-class IP cores deliver the highest performance in the FPGA industry when implemented within Altera's Arria 10 FPGA and SoC.

Arria 10 FPGA and SoC are the industry's most advanced and highest-performance 20nm FPGAs today. These devices feature industry-leading variety of characteristics suitable for meeting high-end, high-performance system requirements.

The industry's only 20nm ARM-based SoC – Arria 10 SoC combines a 1.5GHz dual-core ARM® Cortex™-A9 MPCore™ hard processor system (HPS), embedded peripherals, FPGA logic, DSP blocks, high-speed interfaces and memory, enhancing system integration. The only FPGA with hard-implemented IEEE 754 floating-point DSP - Arria 10 FPGA and SoC can deliver up to 1.5TFLOP of DSP performance, addressing increasingly compute-intensive applications in high-performance computing (HPC), radar, scientific and medical imaging. Highest serial bandwidth - Arria 10 FPGA and SoC provide the industry-leading 3.6Tbps of serial bandwidth with 96 transceiver lanes. This represents both the best-in-class transceiver lanes and bandwidth.