Rapid implementation and verification

The enhanced features of Vivado HLS include improved Quality of Responses (QoR) ranging from C-based synthesis and enrichment to automated AMBA AXI-4 interface inference, enabling time savings and improved integration quality. Because Vivado HLS allows for IP generation and verification directly from C algorithm specifications, it enables the rapid production of designs comparable to hand-coded RTL and verification, tens of times faster than RTL simulation. Used by over 1,000 designers, Vivado HLS also supports a growing ecosystem of hardware-implemented software libraries. The enhanced Vivado Design Suite 2014.3 supports more than 40 OpenCV features and is currently available at Xilinx Technology Ventures portfolio companies and alliance partner Auviz Systems.

Accelerating Integration

The improved Vivado IPI includes automation of connections between streaming and memory-mapped API interconnects, making the process of integrating IP into Zynq SoC-based systems faster and simpler. Additionally, this Vivado IPI newly includes push-button IP evaluation requests for Xilinx Premier Alliance partner IP. The new 2014.3 includes the new Xylon™ logicBRICKS™ evaluation IP core, enabling the addition of other partners in future releases. This new logicBRICKS IP allows for the rapid evaluation of efficient graphics solution IP and further expands the Vivado IP catalog.

Promoting System Design and Software Development

Xilinx extends its Software Development Kit (SDK) with live in-system devices and performance visualizations to rapidly identify system performance bottlenecks and execute anticipated scenarios. Xilinx® SDK 2014.3 provides a configurable AXI traffic generator running on an FPGA fabric, helping to develop embedded software early in the development cycle.

Ultrafast Embedded Design Techniques Guide

To complement the UltraFast design techniques for Vivado, Xilinx has released a new UltraFast Embedded Design Techniques Guide (UG1046). This new guide enables success prediction by providing best practices to design teams (system architects, software engineers, and hardware designers) and improves the productivity of embedded systems using Zynq All Programmable SoCs.

Supply timing

Vivado Design Suite 2014.3 supports Xilinx 7 Series, Zynq All Programmable SoCs, and UltraScale™ devices. Vivado and Xilinx SDKs are available for download at www.xilinx.com/download. New Vivado 2014.3 QuickTake videos are available after signing up for training, and you can improve productivity using UltraFast design techniques and target reference designs based on Vivado Design Suite.