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Xilinx Announces Industry's First Low-Latency 25G Ethernet IP for FPGAs to Solve Data Throughput Challenges in Data Center Applications

Google 우선 소스Published2014.11.19 18:11

New 25G Ethernet MAC and PCS LogiCORE IP Unveiled at Supercomputing 2014

Xilinx Korea (Country Manager Ahn Heung-sik) November 17, 2014 – Xilinx has announced the industry's first low-latency 25G Ethernet IP for FPGAs. This is expected to improve data throughput issues that have long been raised in data center applications. The low-latency 25G Ethernet MAC and PCS LogiCORE™ IP solutions help reduce CapEx in data centers. By providing a migration link from 10G to 25G, it more than doubles the front panel bandwidth between the top-of-rack switch and the server (from 10G to 25G), thereby boosting performance to a groundbreaking level. This unrivaled Xilinx technology supports the new 25G Ethernet Consortium specifications and contributes to the industry's ongoing efforts to advance next-generation processor technology. As part of this next-generation processor technology, Xilinx is also striving for a twofold performance enhancement to open up the future of data center servers.

Meanwhile, Xilinx’s 25G Ethernet MAC and PCS LogiCORE IP will be showcased to customers at Super Computing 2014, held in New Orleans, Louisiana, USA, from November 17 to 20 (Ernest N. Morial Convention Center, Booths #3903 and #4006). In this demonstration, we plan to implement 4-channel 25G Ethernet communication by directly connecting 2 Virtex® UltraScale™ VCU107 boards, a 5m copper cable, and 2 QSFP+ modules.

Usage period
Early test sales of 25G Ethernet MAC and PCS LogiCORE IP solutions are currently underway for select customers. For more information, please contact an authorized Xilinx distributor or visit the Xilinx website at www.xilinx.com/esp/datacenter/data_center_ip.htm .

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