First structurally optimized compiler, libraries, and development boards

Integrated development environment and FPGA runtime environment completely analogous to CPU/GPU

Xilinx Korea (Branch Manager Ahn Heung-sik) November 20, 2014 – Xilinx announced the SDAccel development environment for OpenCL™, C, and C++ at Supercomputing 2014. The new SDAccel development environment leverages FPGA to deliver 25x improved performance per watt for data center applications. SDAccel is a new product in the SDx™ product family and is the industry's first structurally optimized compiler supporting any combination ranging from OpenCL, C, and C++ kernels and libraries to development boards, and integrates an environment that provides development and runtime capabilities completely analogous to CPU/GPU for FPGA for the first time.

Robert Mormuth, CTO at Dell and Director of Platform Architecture and Technology, stated "FPGA-based technology is opening new horizons for optimized computing applications," and added, "Simplified programming is necessary to lower the barriers to adoption of FPGA-based accelerators in Dell server development. Xilinx has clearly demonstrated the right direction for software development environments that enable FPGA platform users to accelerate productivity."

Meanwhile, Brad McCredie, Vice President of IBM's Power Development Division and OpenPower Representative, said "IBM supports the direction Xilinx is taking to expand programming convenience for FPGAs. The flexibility and QoR of optimized FPGA accelerators developed from optimized C, C++, and OpenCL will deliver greater value to customers," and added, "IBM believes OpenCL can help increase productivity, and is continuously working with Xilinx to adopt this technology in OpenPower product designs."

First Structurally Optimized OpenCL, C, and C++ Compiler

SDAccel's structurally optimized compiler delivers up to 25x performance per watt compared to CPU or GPU, and boasts 3x higher performance and resource efficiency compared to other FPGA solutions. Additionally, SDAccel uses basic compiler technology used by over 1,000 programmers. SDAccel leverages the powerful performance of this compiler to enable software developers to achieve significant performance improvements using new or existing OpenCL, C, and C++ code. Memory optimization, data flow optimization, and loop pipelining can be applied across diverse data center applications including search, image recognition, machine learning, transcoding, storage compression, and encryption.

First CPU/GPU Completely Analogous Development Environment for FPGA

Through SDAccel, developers can implement familiar workflows to optimize applications. Additionally, even those without prior FPGA experience can benefit from FPGA platforms. The integrated development environment (IDE) provides coding templates and software libraries, and offers compilation, debugging, and profiling capabilities throughout the entire development process including x86 emulation, fast simulation for performance verification, and basic execution of the FPGA processor. The IDE executes applications on FPGA platforms for data centers with automatic instrumentation capabilities for all supported development targets. Furthermore, SDAccel's architecture helps CPU/GPU developers more easily migrate applications to FPGA, while supporting the maintenance and reuse of OpenCL, C, and C++ code within familiar workflows.

The comprehensive SDAccel environment supports not only a programmer-friendly IDE and C-based FPGA-optimized libraries, but also Commercial Off-The-Shelf (COTS) platforms for data centers.

SDAccel libraries include OpenCL built-ins, DSP, video, high-performance linear algebra libraries, and low power consumption functions. Optimized OpenCV and BLAS OpenCL-compatible libraries for more specialized acceleration are provided by Auvix Systems, a Xilinx Alliance member. Initial COTS members include Alpha Data, Convey, and Pico Computing, with additional vendors expected to register in early next year.

First CPU/GPU Completely Analogous Runtime Implementation Based on FPGA

Only SDAccel supports multiple programs and large applications with on-demand compute units analogous to CPU/GPU. SDAccel provides FPGA solutions while maintaining CPU/GPU similarity, preserving system functionality during program switching. SDAccel is the only environment capable of generating FPGA-based compute units that allow new accelerator kernels to be applied while existing applications are running. While applications are executing, critical system interfaces and functions such as memory, Ethernet, PCIe®, and performance monitoring continue to operate. Through dynamically reconfigurable compute units, FPGA accelerator functions can be shared across multiple applications. For example, image search with operating system programming, video transcoding, and image processing can be performed alternately.

Availability

SDAccel will be demonstrated at Supercomputing 2014 being held in New Orleans today (Booth 3903). For detailed information on SDAccel trial products, contact Xilinx's official distributors or visit the Xilinx website at www.xilinx.com/sdaccel.

The public specifications of this product are based on the Khronos Specification, and are expected to pass the Khronos Conformance Testing Process. Current specification compliance status can be verified at www.khronos.org/conformance.

SDx Overview

SDx is a suite of development environment products for system and software developers. SDx enables developers without prior FPGA experience to leverage the powerful performance of industry-standard programmable hardware using high-level programming languages. More detailed information about SDx is available at www.xilinx.com/sdx.