– Implementation of the unique functionality of the JESD204B SERDES high-speed interface with a new clock IC

December 3, 2014 – Analog Devices ( www.analog.com , NASDAQ: ADI), a global leader in high-performance semiconductors for signal processing applications, has released the AD9528 JESD204B clock and SYSREF generator, suitable for supporting the clock requirements needed for LTE and multi-frequency GSM base station designs, defense electronics systems, RF test instrumentation, and other emerging broadband RF GSPS data acquisition signal chains. As data rates increase to the range of several Gb per second and multi-channel synchronization and data latency management become essential components of systems, the JESD204B standard is increasingly being used for high-speed interfaces from converters to digital processors across various modern applications. The JESD204B interface was specifically developed to address the growing need for high-data-rate system designs, and the AD9528 clock device includes features to support and enhance the inherent performance of such interface standards.

The AD9528 supports clock distribution with low power, multiple outputs, and low-frequency performance, as well as on-chip, 2-stage PLL and VCO. The on-chip VCO adjusts the frequency between 3.6 GHz and 4.0 GHz through an input receiver and oscillator that provide both single-ended and differential operations.

The AD9528 provides JESD204B compliant subclass 1 SYSREF and deterministic latency clocking signals and offers various options for generating SYSREF signals. The most basic function is a simple buffering feature where the user-provided SYSREF signal is spread to the SYSREF output pin. If an external SYSREF source is provided, the AD9528 can also synchronize the SYSREF output with the internally generated clock output, which is essential to achieve precise deterministic delay. The AD9528 can also generate the SYSREF source internally. The AD9528 supports both continuous-signal SYSREF generation and n-shot pulse generation. N-shot generation is mandatory for systems where a continuous signal may cause unwanted spurts in the output spectrum of the clock-provided data converter.

When connected to a recovered system reference clock and VCXO, the AD9528 generates 12 low-noise outputs ranging from 1 MHz to 400 MHz and 2 high-speed outputs at speeds up to 1.25 GHz. To vary the frequency and phase of a single clock output relative to other clock outputs, a divider phase-select function can be used, providing jitter-free coarse timing adjustment as the period of the signal from the VCO output increases by half. Each SYSREF signal provides additional phase offset performance, making it easier to adjust for the optimal arrival time at each target device.

The design of the AD9528 can be implemented using ADI's AD9680 dual-channel, 14-bit, 1.0 GSPS JESD204B A/D converter within a broadband RF data acquisition application.

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