Applied Materials, a global leader in semiconductor and display materials engineering solutions, announced next-generation semiconductor manufacturing equipment designed to maximize AI computing performance, accelerating innovation in AI semiconductor manufacturing.

On the 26th, Applied Materials introduced the Kinex bonding system, the Centura Xtera epi system, and the PROVision 10 electron beam metrology system, targeting key areas of the AI chip development competition, such as advanced logic based on GAA (gate-all-around) transistors, HBM (high-bandwidth memory) DRAM, and advanced packaging for implementing high-density 'system in package (SiP)'.

Today's GPUs and HPC chips use advanced packaging methods that combine multiple chiplets.

To support this, Applied Materials, in collaboration with Besi, has introduced the industry's first die-to-wafer hybrid bonder integrated system, Kinex.

This system improves performance and reduces power and costs through direct copper-to-copper bonding, and enhances bonding quality and consistency through process step integration. It also supports overlay measurement and drift detection with inline measurement.

Kinex systems are already in use by numerous logic, memory, and OSAT customers.

Additionally, Applied has developed the Centura Xtera epi system to form the source/drain structure that determines the performance of next-generation GAA transistors.

This system reduces gas usage by 50% with its unique low-capacity chamber structure, and improves cell-to-cell uniformity by more than 40% through the implementation of a void-free source/drain structure and deposition-etch process.

The Xtera system is being adopted by leading-edge logic and memory chip manufacturers to enhance stability and performance in sub-2nm processes.

Applied Materials also improves yields for advanced logic and memory chips with the PROVision 10 electron beam metrology system.

This system is the first in the industry to use Cold Field Emission (CFE) technology, and offers a 50% increase in resolution and a 10-fold improvement in imaging speed compared to existing systems.

It also enables 3D chip multilayer imaging and sub-nanometer precision measurements.

This system is essential for key process control, including EUV layer overlay, GAA transistor nanosheet measurement, and epi void detection.

“The proliferation of 3D architectures presents new metrology challenges,” said Keith Wells, vice president of Applied Materials. “PROVision 10 is a powerful tool for improving yields of complex chip designs.”

“As chips become more complex, we need to improve the performance and power efficiency needed to scale AI,” said Prabu Raja, president of Applied Materials’ Semiconductor Products Group.“We are focusing on innovation in materials engineering,” he said, adding, “We are working with our customers to jointly develop solutions that enable technological leaps in logic, memory, and packaging.”