Domestic researchers have achieved a result that significantly exceeds the performance limits of 3D stacked DRAM by combining a laser crystallization process and a heterogeneous channel design.

Professor Hyun-Yong Yoo of Korea University and Professor Hyuk-Joon Kwon's team at DGIST announced on the 17th that they have implemented a complementary gain cell (CGC) structure by vertically stacking a silicon layer (p-Si) and an oxide semiconductor (n-IGZO) made by pattern-based seedless laser crystallization (PSLC) for the first time in the world, thereby simultaneously boosting the speed and sensing capabilities of 2T0C DRAM.

The research team secured a grain size of 32.3 µm through a laser process, and as a result, the hole mobility reached 265 cm²/Vs.

In addition, by utilizing the capacitive coupling between devices, which was previously pointed out as a problem, in reverse to obtain a voltage amplification effect, the sensing margin was improved to a level of tens to hundreds of times compared to the previous one.

Simulation and measurement results showed that the read delay was about 11.8ns, which is about 7.6 times faster than an IGZO-only cell (about 90.1ns), and reliability was also verified by securing a retention time of more than 1,000 seconds.

Since all processes are carried out at 400℃ or below, memory layers can be stacked without damaging the underlying logic, allowing for monolithic 3D (M3D) It is also noteworthy that it is suitable for integration.

The research team expected this technology to be a significant turning point in the commercialization of high-density, high-performance memory and memory solutions for AI chips.

This research was accepted to the VLSI Technology Symposium 2026 and was conducted with support from the Ministry of Science and ICT and the National Research Foundation of Korea.