Samsung Electronics unveiled next-generation 3D memory architecture mockups for the first time, solidifying its technology strategy to address AI infrastructure demands. By presenting vertical integration structures that transcend the physical limitations of conventional stacking methods and ultra-high-layer NAND technology, the company demonstrated its memory technology competitiveness.

Samsung Electronics announced that it displayed mockups of next-generation 3D memory architecture zHBM and zNAND-O at 'FMS (Future of Memory and Storage) 2026' held at the Santa Clara Convention Center in California on August 4-6, with the unveiling on August 5.

Lee Jin-yeop, Vice President of the Flash Development Division, and Kim Gyeong-ryun, Executive Vice President of the DRAM Development Division, delivered keynote speeches introducing next-generation memory technology vision and AI infrastructure response roadmap.

zHBM is a next-generation architecture that vertically stacks HBM on top of AI accelerators (xPU), reducing data movement distance compared to the conventional method of placing HBM beside accelerators, thereby enhancing bandwidth and power efficiency.

According to Samsung Electronics, systems employing zHBM deliver up to 8x higher performance compared to HBM5, improve power efficiency by up to 3x, and reduce thermal resistance by over 50%.

By adding customized IP (Intellectual Property) to the interlayer, customer-tailored design is also possible, including memory capacity expansion and accelerator performance enhancement.

zNAND-O is a high-performance NAND solution that combines TSV (Through Silicon Via) with existing V-NAND vertical stacking technology to achieve 3D packaging of 4-tier or 8-tier chips.

Optimized for on-device AI environments, Samsung Electronics explained that the product supports real-time large-scale data processing based on high space efficiency and fast response speed.

At this event, Samsung Electronics also unveiled the 10th generation V-NAND 'V10 BV-NAND' featuring a vertical stacking structure of over 400 layers.

By applying wafer bonding technology and 3 Stack technology, the company increased memory integration density by approximately 58% compared to the previous generation (V9), and also improved data read/write performance and I/O speed.

Next-generation memory and storage portfolio was also showcased.

The company exhibited △HBM4E △HBM5 mockups △LPDDR5X-PIM △PM1763 △BM1773 and others.

In particular, Samsung Electronics introduced LPDDR5X-PIM as a product that performs computations within memory to reduce data movement and enhance power efficiency.

Samsung Electronics emphasized its 'one-stop solution' capability to provide integrated support from customer design stages to mass production based on its comprehensive semiconductor (IDM) system encompassing memory, logic, foundry, and packaging.