TI Launches 1.25GSPS, 16-bit DAC Reducing Power Consumption by 65% and Improving Speed by 25%

3G/LTE/WiMAX base stations and repeaters, and SDR (Software Defined Radio)
Provides best-in-class energy efficiency, speed, and size

TI Korea (CEO Jaejin Kim, www.ti.com/ww/kr ) March 25, 2011 – TI announced the DAC3484, a 4-channel 16-bit Digital-to-Analog Converter (DAC) with the industry's highest power efficiency. The DAC3484 offers a 25% speed improvement over the second-fastest 4-channel DAC under the same conditions at 1.25 GSPS, while reducing power consumption by 65% compared to the most similar competitors, consuming a minimum of 250mW per channel. Additionally, the DAC3484 supports broadband power amplifier linearity of up to 250MHz, despite being more than 40% smaller than competing 4-channel DAC solutions. The DAC34H84, featuring a wider input bus supporting linearity bandwidth of up to 500MHz, and the 2-channel DAC3482 are also available. (For sample orders and more information about the product, please refer to www.ti.com/dac3484-prkr )

Steve Anderson, Senior Vice President of TI’s High Performance Analog Business Unit, stated, “Wireless base station manufacturers face the technical challenge of providing systems that can increase bandwidth and performance while keeping power consumption low,” adding, “The DAC3484 and two related DACs help customers designing 3G/LTE/WiMAX base stations, broadband repeaters, and Software Defined Radio (SDR) optimize system energy efficiency in a smaller footprint.”

Key Features and Advantages
• 16-bit interleaving 1.25GSPS input reduces the number of I/Os by half, lowering FPGA costs and simplifying board routing.
• The 9mm x 9mm Multi-row QFN package enables higher density main and diversity transmitters.
• 2 to 32 times low-jitter PLL (Phase Locked Loop) optimizes multiplier function by eliminating the external low-jitter clock for interpolated rate matching.
• 2–16x interpolation capabilities and two independent 32-bit NCOs (Numerically Controlled Osscillators) reduce FPGA interface speed and cost while providing flexibility for frequency variations.
• Offset, gain, group delay, and phase control functions for system correction are direct Significantly improved sideband suppression characteristics for broadband signals used when interfacing with IQ modulators such as the TRF372017 in up-conversion wireless.

Tools and Support

The Evaluation Module (EVM) is currently available for $499. The DAC3484EVM, DAC3482EVM, and DAC34H84EVM include TI's power management devices, such as DC/DC converters and low-noise LDOs, as well as the TRF370315 IQ modulator and CDCE62005 clock jitter cleaner, to support complete bit-to-RF prototyping and reference design. The EVM can also be tested with the GC5330SEK, a complete transmit/receive and digital pre-distortion system evaluation kit and reference design for power amplifier linearity.

In addition, the TSW3100 pattern generation module features a high-speed dual-rate Low-voltage differential signaling (LVDS) data output bus that provides 16-bit data at a rate of 1.25 GSPS per bit. When integrated with the DAC3484EVM, the TSW3100 supports data pattern generation functions with ease while enabling flexible evaluation.