HLx complements the SDx environment to provide reusable, all-programmable

Xilinx announced the release of the Vivado® Design Suite HLx Edition, which provides the highest productivity in the design of all-programmable SoCs and FPGAs and the development of reusable platforms.

The new HLx editions include the HL System Edition, HL Design Edition, and HL WebPACK™ Edition. All of these HLx editions include Vivado High-Level Synthesis (HLS), which enables easy utilization of the most productive and cutting-edge C and IP-based design flows, including C/C++ libraries, Vivado IP Integrator (IP Integrator), LogicCORE™ IP subsystems, and the full Vivado implementation tool suite.

When used with the new UltraFast™ High-Level Productivity Design Methodology Guide, users can achieve 10 to 15 times higher productivity than with traditional methods, and this HLx edition can be upgraded for free from Vivado Design Suite.

Increase productivity through reusable platform development and programming

Over the past three years, advanced Xilinx customers have pioneered and advanced the C and IP-based design technologies and methodologies currently included in the HLx edition, demonstrating 10 to 15 times the potential productivity. To achieve this productivity, customers adopted all or part of 1) C-based design and optimized reuse, 2) IP subsystem reuse, 3) integration automation, and 4) accelerated design finishing.
Unlike conventional RTL-based designs, where most of the design is consumed in the final stages of the design process, C and IP-based designs offer exceptional design reusability, accelerating development and enabling rapid design exploration for better detailed architectures. This replaces error-prone manual C to RTL conversion, reduces the time and errors involved in integrating C and RTL-based IP, and significantly shortens verification time. Customers can quickly achieve overall superior or equivalent quality results (performance, power, and utilization) by utilizing high-level abstraction.

To support such high productivity, the HLx edition includes Vivado HLS, Vivado IPI, the LogicCORE IP subsystem, and the entire Vivado implementation tool suite. Additionally, Xilinx and its alliance ecosystem are continuously expanding market-specific C libraries, such as OpenCV for video and image processing, machine learning for Advanced Driver Assistance Systems (ADAS), and data center applications.

Xilinx's new LogiCORE IP subsystem is a highly configurable, market-tailored building block that integrates up to 80 individual IP cores, software drivers, design examples, test benches, and more. This new IP subsystem can be used for Ethernet, PCIe®, video processing, image sensor processing, and OTN development. In addition, the IP subsystem ensures interoperability with Xilinx and Alliance member IPs and accelerates integration speed based on industry standards such as AMBA® AXI 4 interconnect protocol, IEEE P1735 encryption, and IP-XACT.

C-based IP and pre-packaged IP subsystems are rapidly combined using the Vivado IP Integrator for integration automation. Vivado IPI's integration automation supports intelligent automatic connection of core IP interfaces, one-click IP subsystem creation, real-time DRC, and the ability to deliver interface changes, along with powerful debugging capabilities, all through an interactive environment that recognizes devices and platforms.

This platform-aware intelligence can support target boards by pre-configuring Zynq® SoC and MPSoC processor systems with accurate peripherals, drivers, and memory maps. Design teams can now rapidly identify, reuse, and integrate software and hardware IP targeting ARM® processor systems and high-performance FPGA logic.

Tom Feist, Senior Director of Design Methodology Marketing at Xilinx, stated, “HLx Edition provides a framework for the development and programming of a reusable, all-programmable platform,” adding, “By providing advanced tools, IP, and UltraFast design methodologies in all Vivado packages, most Xilinx customers have been able to focus on value differentiation and achieve better designs faster.”

Development and deployment of the platform by complementing HLx and SDx

HLx accelerates the time required for hardware engineers to develop, modify, and program all-programmable platforms, and complements the Xilinx SDx development environment (SDSoC™, SDAccel™, SDNet™) for software and system engineers. The SDx product family's development environment enables software-defined programming of the HLx generated platform by using a mix of C, C++, OpenCL, and the modern P4 language for packet processing. HLx and SDx represent a new generation of Xilinx's design enablement solutions for developing smarter, more connected, and differentiated systems by leveraging next-generation all-programmable devices, including Zynq SoCs, MPSoCs, ASIC-class FPGAs, and 3D ICs.

Upgrades to the Vivado Design Suite HLx Edition can be performed from the Vivado Design Suite 2015.4 release, which supports Xilinx 7 Series and UltraScale™ and UltraScale+™ devices. You can also download the latest release from the website www.xilinx.com/download . For more information, refer to Vivado Quicktakes videos and training registration, the Ultra-Fast Design Methodology Guide for Vivado Design Suite, and the Ultra-Fast High-Level Productivity Design Methodology Guide for the New Vivado Design Suite.