Xilinx provides extensive support for 7-Series FPGAs with ISE Design Suite 13 and delivers system-level productivity enhanced by the new Team Design Flow.

With innovative tools using open industry standards and plug-and-play IP improvements
Accelerate design, production, verification, implementation, and lower system power

Xilinx Korea (Country Manager Heung-Sik Ahn) March 14, 2011 – Xilinx announced the ready-to-use ISE® Design Suite, ISE 13. This award-winning design tool and IP suite has been improved to enhance the productivity of SoC design teams and advance true plug-and-play IP targeting Spartan®-6, Virtex®-6, and 7 Series FPGAs, including the industry-leading 2 million-logic-cell Virtex®-7 2000T device. Focusing on reducing development time and costs, ISE Design Suite 13 introduces accelerated verification methods, such as IP-XACT-enabled plug-and-play IP and a new team design approach that shortens design cycles by allowing multiple engineers to work in parallel.

Xilinx offers FPGAs with millions of system gate capacities, such as the Virtex-7 2000T, built using stacked silicon interconnect technology. Furthermore, productivity becomes the most critical factor in such complex designs because a single FPGA not only handles serial, parallel, and digital signal processing but also provides transceivers with speeds up to 28 Gbps. According to the international technology roadmap for semiconductors, companies must achieve a cycle time improvement of more than 50% to stay on the productivity curve. If the time required for verification exceeds half of the total design time, the verification team can achieve direct productivity improvements through the new hardware cosimulator and AMBA4 and AXI4 bus function simulation models of ISE Design Suite 13.

Accelerated verification
Through Xilinx’s portfolio of development boards, kits, and ISE simulators, design teams have been able to accelerate simulation execution from hours to minutes. By simulating the currently implemented blocks in real-time while leaving other blocks under development untouched, full verification can be completed approximately 100 times faster than with conventional simulation methods. The newly added AX14 bus function model can also be added to verification test benches to drive stimulus and validate the interconnection logic of customer-supplied IP, thereby improving overall productivity.

New Team Design Flow
In addition, ISE Design Suite 13 is a team design method that can solve the difficulties of multiple engineers working on a single project by providing a method for groups of developers working in parallel (see Increased Productivity Using Team Design).

Tom Feist, Senior Marketing Director at Xilinx ISE Design Suite, stated, “Because SoC design is complex, it may require an international team of developers working on a single design. Not only are multiple engineers developing the HDL, but a separate engineer may also act as an integrator responsible for the synthesis and implementation of the entire system design.” "To foster a sense of challenge, this team can be organized into several companies that develop different modules of the design," he said.

Along with the Design Preservation feature implemented in ISE Design Suite 12, Team Design Flow provides several additional capabilities. It also allows for the pre-implementation and lockdown of parts of the overall design without waiting for design results from other teams. Furthermore, advanced optimization techniques, such as intelligent clock gating technology that can reduce dynamic power by up to 30%, make timing easier to achieve. By preserving timing across the rest of the design, overall productivity is improved and design iterations are reduced.

IP-XACT supported plug-and-play IP
By accelerating design reuse, the new ISE Design Suite 13 now provides new open standards consistent with Xilinx’s Plug-and-Play initiative (see AXI4 interconnects facilitating Plug-and-Play IP), shortening design time by facilitating IP development for Xilinx and third parties. This announcement introduces an option to reduce silicon usage by approximately 50% by designing with fewer connections than those used in the existing AXI4. For high-performance AXI4 systems, customers can achieve up to 20% higher system bandwidth for interconnect and memory interfaces. Users can now customize their systems in terms of performance or domain to achieve optimal system topologies.

In addition, Xilinx provides a new IP-XACT-based IP packager for the Alliance program. The IP-XACT-based IP packager provided by Xilinx enables Alliance members to package their IP, allowing for easy access from the Core Generator™ IP repository. IP-XACT enables a consistent user experience for using IP from both Xilinx and Alliance program members. In ISE Design Suite 13.1, 50 Xilinx IP cores support IP-XACT, and within one year, all Xilinx IP cores will support IP-XACT. In future announcements, this same capability will be made available to customers for the easy design reuse of their IP.

A member of the Premier Xilinx Alliance Program and Northwest Logic (Northwest Lo