Altera Provides Industry's First Interface Targeting MoSys Serial High-Density Bandwidth Engine Devices

Support for the GigaChip Interface on the Stratix IV GT FPGA provides a proven high-performance serial memory solution to 100G wired application developers.

Hong Kong, February 10, 2011 – Altera Corporation (Nasdaq: ALTR) announced today that it has successfully completed interoperability testing between its Stratix® IV GT FPGA and MoSys’ Bandwidth Engine® devices in serial memory applications. By interoperating with MoSys’ Bandwidth Engine devices using the GigaChip™ Interface, the Stratix IV GT FPGA provides high-performance, high-bandwidth memory solutions to designers of 100G wired applications, such as traffic management and packet processing. Altera has become the first FPGA vendor to offer devices supporting the GigaChip Interface through its Stratix IV GT FPGA.

Altera is a founding member of the MoSys GigaChip Alliance, which includes semiconductor companies collaborating to support high-efficiency serial chip-to-chip communication in next-generation high-performance networking, computing, and storage systems. The GigaChip Interface utilizes transceiver technology to provide innovative chip-to-chip communication performance. MoSys is utilizing Stratix IV GT FPGAs for the development of the GigaChip Interface as Altera provides high-performance transceiver technology in a timely manner.

David DeMaria, Vice President of Business Operations at MoSys, stated, “The GigaChip Interface provides four times the bandwidth density compared to DDR-type interfaces while reducing system power and interface costs by two to three times. Our goal is to establish this as an open industry standard capable of supporting high-efficiency chip-to-chip communication, and we are pleased to announce the industry’s first interoperability with Altera. The transceiver technology provided by the Stratix IV GT FPGA offers MoSys an ideal platform to implement Bandwidth Engine interfaces and controllers. Through Altera’s proven transceiver technology combined with the Stratix IV GT FPGA, we are now able to provide customers with high-performance serial memory solutions targeting next-generation networking systems.”

The GigaChip Interface is a short-range, low-power serial interface that supports high-efficiency, high-bandwidth, low-latency performance. The Stratix IV GT FPGA utilizes the GigaChip Interface through the device's soft memory controller, which maximizes design flexibility, and the device's 11.3Gbps transceiver.