Altera Corporation today announced the Stratix® V FPGA family, featuring the industry's widest bandwidth with 28-nanometer technology. The Stratix V FPGA, delivering up to 1.6Tbps (1.6 terabits per second – terabit equals one trillion bits) of serial switching capability, leverages numerous new technologies and state-of-the-art 28-nanometer process technology to significantly reduce cost and power consumption for high-bandwidth applications.

Manufactured on TSMC's 28nm high-performance process, the Stratix V FPGA family offers up to 1.11 million logic elements (LEs), 53 megabits of embedded memory, 3,680 18x18 multipliers, and integrated transceivers with industry-leading maximum operating speeds reaching 28Gbps.

These devices also feature industry-leading hardened hardware IP tailored for each application, improving system integration and performance without increasing cost or power consumption. The product family comprises four variants designed for diverse applications across wireless/wireline communications, military, broadcast, computing and storage, test, and medical markets.

Stratix V GT FPGA – The industry's only FPGA with integrated 28Gbps transceivers for 100 gigabit and beyond systems
Stratix V GX FPGA – Features transceivers ranging from 600Mbps to 12.5Gbps to support diverse applications
Stratix V GS FPGA – Contains transceivers ranging from 600Mbps to 12.5Gbps and optimized for high-performance digital signal processing (DSP)
Stratix V E FPGA – High-density FPGA ideal for ASIC prototyping, emulation, and high-performance computing applications

Vince Hu, Vice President of Product and Corporate Marketing at Altera, stated, "The density and I/O performance of our fifth-generation Stratix product family, our high-end devices, have increased dramatically, widening the competitive gap between ASIC/ASSP and FPGA." He added, "Altera will continue to pursue the challenging objective of steadily increasing bandwidth while meeting cost and power requirements. We have carefully considered every aspect from core to I/O to ensure Stratix V FPGA delivers the highest level of performance, density, and integration."

Stratix V FPGA Engineered for Bandwidth
Stratix V GX and Stratix V GS FPGAs feature 66 high-performance, low-power transceivers with maximum operating speeds reaching 12.5Gbps. Stratix V FPGA complies with all 3G, 6G, and 10G protocols and meets electrical standards such as 10G/40G/100G, Interlaken, and PCI Express® (PCIe®) Gen3, Gen2, and Gen1. These devices also provide direct interoperability with 10G backplane (10GBASE-KR) and optical modules. The 28Gbps transceivers in Stratix V GT FPGA are designed to satisfy the CEI-28G specification and consume only 200mW (milliwatts) per channel, dramatically reducing power consumption relative to bandwidth.

Beyond transceiver bandwidth, Stratix V FPGA features interfaces accommodating seven 72-bit DDR3 memory modules at 1.6Gbps speed and LVDS channels capable of operating at 1.6Gbps with ubiquitous I/O.
Altera has made several improvements to the core architecture of Stratix V FPGA to enhance logic efficiency, including the following items.

New Adaptive Logic Module (ALM) – The largest devices include up to 800,000 additional registers to maximize logic efficiency. ALM architecture is ideal for designs requiring extensive pipelining and registers.

Enhanced embedded memory structure with M20K blocks – Provides higher area efficiency and performance
Industry-first DSP blocks with variable precision floating-point arithmetic – Delivers optimal performance and efficiency across multiple precision DSP data paths
User-friendly partial re-configuration – Enables designers to reconfigure portions of the FPGA while keeping other parts operational.

Additional information on Stratix V FPGA architecture is available at www.altera.com/strarix5.

Stratix V FPGA integrates more hardened hardware IP than any other FPGA, increasing device capabilities without adding power consumption or cost. Hardened IP-integrated functions include PCIe Gen3, Gen2, Gen1, 40G/100G Ethernet, CPRI/OBSAI, Interlaken, Serial RapidIO® (SRIO) 2.0, and 10GBASE-R (10 gigabit Ethernet).