Altera, regarding customers' diverse design requirements
Announcement of Customized 28nm Device Portfolio

By providing the widest variety of products in the industry
Meeting expanding system requirements for performance, power, and cost

Hong Kong, January 25, 2011—Altera Corporation (NASDAQ: ALTR) today announced its 28nm device portfolio, enabling it to provide the industry's most comprehensive set of device options tailored to the diverse design requirements of its customers. Through the new Cyclone® V and Arria® V FPGA families, the recently expanded Stratix® V FPGA family, and the previously announced HardCopy® V ASIC, Altera is providing customers with clearly differentiated solutions.

By maintaining long-standing, close partnerships with industry leaders, Altera possesses a deep understanding of the unique performance, functionality, and power requirements essential for a wide range of applications, from the highest bandwidth to the lowest power. Leveraging its advantages in transceiver technology, product architecture, intellectual property (IP) integration, and process technology with this 28nm portfolio, Altera provides optimized solutions to address the various design challenges faced by its customers.

Altera is customizing these advantages for diversification in the following ways:

• Transceivers—Altera has optimized its proven, industry-leading transceiver technology to match the performance range of each 28nm device family. Altera's 28nm devices support transceiver speeds from 600Mbps to 28Gbps.
• Product Architecture—On-chip memory optimized for performance and efficiency; hard and soft memory controllers capable of supporting the bandwidth performance and cost requirements of necessary applications; high-end, mid-range, and low-cost I/O optimized for performance.
• IP Integration—To meet customers' cost, power, and performance requirements, Altera provides various system-level IPs as hard IPs, such as PCI Express® (PCIe®) Gen2 x1 and x4, PCIe Gen3 x8, Interlaken, 40G/100G, and 100 Gigabit Ethernet (100GbE).
• Process Technology—To effectively support the widest range of applications, Altera utilizes TSMC’s 28HP (28-nm High Performance) process technology for its high-end product families (Stratix V FPGA) and HardCopy V ASICs, and TSMC’s 28LP (28-nm Low-Power) process technology for its low-cost (Cyclone V FPGA) and mid-range (Arria V FPGA) product families. The 28LP process also enables Altera to provide an optimal balance of cost, performance, and low power. Using 28HP process technology for the high-end product family is critical to providing the core and transceiver performance required by high-end applications.

Altera's Cyclone V FPGA family is optimized for applications such as motor control, displays, and software-defined radio (SDR) where low power consumption and board space are key concerns. The Cyclone V family offers 40% lower overall power consumption compared to previous generation devices, 12 transceivers operating at up to 5Gbps, a hard PCIe Gen2 x1 block, and a hard memory controller supporting LPDDR2, mobile DDR, and DDR3.

Detailed information about the Cyclone V product family can be found at www.altera.com/cyclonev .
Altera has announced its Arria V FPGA family, targeting applications such as remote wireless units (RRUs), in-studio mixers, and 10G/40G line cards that require a balance of price, low power, and high performance. The Arria V FPGA family includes a hard memory controller supporting DDR3 external memory and an efficient finite impulse response (FIR) filter that provides variable-precision DSP blocks, enabling up to 40% reduction in total power compared to previous generation devices. More information about the Arria V family can be found at www.altera.com/arriav .

The Stratix V FPGA family supports a wide range of high-bandwidth applications, such as advanced LTE base stations, high-end RF cards, and military radar. Altera has expanded the performance of the Stratix V family to meet evolving market requirements. The maximum transceiver data transfer speed of the Stratix V GX FPGA has been improved to 14.1 Gbps, enabling support for new high-speed protocols such as FiberChannel 1600. Furthermore, the integration density of the Stratix V GX FPGA is a monolithic die (mo