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2MHz ~ 2700MHz Clock, Multi-Chip Synchronization JESD204B Clocking Capability Provided
Linear Technology Korea (CEO Hong Sa-gwak) has announced the launch of a low phase noise integer-N synthesizer with an integrated VCO and ultra-low jitter clock distribution section (product name: LTC6951).
This product is ideal for providing clocks to data converters. The LTC6951 provides four high-performance CML (current mode logic) outputs, and each output is equipped with an independent low-noise clock divider and digital delay block, covering a wide frequency range between 1.95MHz and 2700MHz.
With a total absolute jitter value of 115fsRMS (SNR technique), the LTC6951 provides an essential low-jitter clock for achieving the highest level of SNR when providing clocks to data converters at fast input frequencies and high-speed output data rates.

The LTC6951 has introduced three AI-type circuits that can simplify the design of large-scale clock trees necessary for systems with multiple daughter cards or large-scale data converters, including output clock expansion.
Linear Technology's proprietary EZSync™ output synchronization technique ensures a repetitive and deterministic phase relationship between all clock divider outputs in the LTC6951 and follows EZSync-supported devices. Through the ParallelSync™ multi-chip parallel synchronization function, outputs for multiple LTC6951 ICs are retimed to a common reference clock.
These features allow synchronization of reference adjustment with a reference clock domain that easily meets setup and hold time requirements in the nanosecond range. The EZ204Sync™ synchronization technique, which complies with JESD204B subclass 1, is built on the basis of two existing methods and can generate the SYSREF and DEVCLK signals essential to the JEDEC standard between multiple LTC6951s connected in parallel and other EZSync-compatible clock devices.
Designing with the LTC6951 is simple using the LTC6951Wizard™ simulation and design tool, which can be downloaded free of charge from www.linear.com/LTC6951Wizard. The LTC6951Wizard software provides appropriate PLL settings and loop filter component values with a single button click and precisely predicts phase noise and jitter of individual outputs.
Beyond performance simulation, the LTC6951Wizard GUI provides scope plot features that simulate time-domain results of LTC6951 outputs based on clock divider, delay, and synchronization settings, simplifying the design process and providing support in the circuit debugging phase.
The LTC6951 is guaranteed to operate over the full operating junction temperature range of −40°C ~ 105°C. This product is available in a space-saving 5mm × 7mm, 40-pin plastic QFN package. The LTC6951 is priced at $8.75 per unit based on quantities of 1,000 and is available immediately.
Linear Technology Korea (CEO Hong Sa-gwak) has announced the launch of a low phase noise integer-N synthesizer with an integrated VCO and ultra-low jitter clock distribution section (product name: LTC6951).
This product is ideal for providing clocks to data converters. The LTC6951 provides four high-performance CML (current mode logic) outputs, and each output is equipped with an independent low-noise clock divider and digital delay block, covering a wide frequency range between 1.95MHz and 2700MHz.
With a total absolute jitter value of 115fsRMS (SNR technique), the LTC6951 provides an essential low-jitter clock for achieving the highest level of SNR when providing clocks to data converters at fast input frequencies and high-speed output data rates.
The LTC6951 has introduced three AI-type circuits that can simplify the design of large-scale clock trees necessary for systems with multiple daughter cards or large-scale data converters, including output clock expansion.
Linear Technology's proprietary EZSync™ output synchronization technique ensures a repetitive and deterministic phase relationship between all clock divider outputs in the LTC6951 and follows EZSync-supported devices. Through the ParallelSync™ multi-chip parallel synchronization function, outputs for multiple LTC6951 ICs are retimed to a common reference clock.
These features allow synchronization of reference adjustment with a reference clock domain that easily meets setup and hold time requirements in the nanosecond range. The EZ204Sync™ synchronization technique, which complies with JESD204B subclass 1, is built on the basis of two existing methods and can generate the SYSREF and DEVCLK signals essential to the JEDEC standard between multiple LTC6951s connected in parallel and other EZSync-compatible clock devices.
Designing with the LTC6951 is simple using the LTC6951Wizard™ simulation and design tool, which can be downloaded free of charge from www.linear.com/LTC6951Wizard. The LTC6951Wizard software provides appropriate PLL settings and loop filter component values with a single button click and precisely predicts phase noise and jitter of individual outputs.
Beyond performance simulation, the LTC6951Wizard GUI provides scope plot features that simulate time-domain results of LTC6951 outputs based on clock divider, delay, and synchronization settings, simplifying the design process and providing support in the circuit debugging phase.
The LTC6951 is guaranteed to operate over the full operating junction temperature range of −40°C ~ 105°C. This product is available in a space-saving 5mm × 7mm, 40-pin plastic QFN package. The LTC6951 is priced at $8.75 per unit based on quantities of 1,000 and is available immediately.
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