Heterogeneous products for multicore SoC design
A configurable and highly scalable distributed architecture

Arteris, a SoC interconnect IP specialist dreaming of becoming the next ARM, has thrown down the gauntlet to ARM with Cache Coherent.

Arteris announced the release of version 1.5 of its Ncore cache coherent interconnect IP. Prior to the announcement, Branch Manager Yeon Myeong-heum emphasized the importance of the product, stating that cache coherent represents "another realm" and is a "groundbreaking product" that will "serve as an opportunity for Arteris to take another leap forward."

Ncore IP is a distributed heterogeneous cache coherent interconnect product that supports efficient designs suitable for entire coherent systems by offering system designers the advantage of being able to configure multiple snoop filters and embedded caches. The company stated that Ncore IP provides significantly more flexible performance than the fixed or centralized cache coherent interconnects typically used in SoC designs.

▲ David Kruckemyer, Chief Executive of Hardware Design

The cache creates copies of the data, but it is difficult to manage these copies with software. In contrast, hardware cache coherence has the advantage of creating a virtual, flat shared memory where multiple copies are stored consistently. However, copy management in hardware requires extensive communication because it must check every possible location where a valid copy might exist.

Optimization of system performance, power consumption, and cost is possible, and timing closure is also easy.

Ncore's unique heterogeneous cache coherence supports multiple coherence models and allows the use of multiple configurable snoop filters to accommodate different cache configurations.

During his visit to Korea, David Kruckemyer, Chief Hardware Design Officer, stated, “The coherent agent interface can transform individual coherence models into general models,” adding, “Related cache agents that share common attributes with individual snoop filters occupy less die area than a single snoop filter.”

In particular, the adoption of a modular approach with configurable settings is another advantage. Executive David explained, “With transaction processing and data bandwidth control capabilities, each component can be adjusted individually, and ports per component can be controlled separately,” adding, “This allows for achieving target performance without wasting resources and enables easy adjustment of the system design even as requirements change.”

In other words, Ncore interconnect IP improves configurability in SoC designs by simultaneously realizing the implementation of different coherent protocols, cache state models, and cache configurations. Accordingly, the company stated that this product is suitable for implementing heterogeneous cache coherent SoC designs for rapidly changing market environments such as wireless mobility, HDTV, enterprise storage, automotive ADAS (advanced driver assistance systems), microservers, and networking.

Ncore Interconnect IP version 1.5 supports one to eight full coherent agent ports, multiple snoop tag filters with adjustable size and agent coupling rates, and a configurable embedded proxy cache (I/O cache). Because Ncore has ample room for significant advancement beyond the feature set of version 1.5 in terms of its architecture, it is possible to design a more robust next-generation Ncore product roadmap.

Furthermore, Executive David, who compared the Ncore interconnect to fixed or hub-based cache controller implementations, stated, “It is characterized by a distributed solution consisting of replicators and core components,” adding, “This supports scalability so that the interconnect IP meets various processing requirements.”

He added, “It requires less space for cache coherent interconnects and, as a modular Ncore component, can be placed close to critical IP, minimizing power distribution congestion.”

The full video is available for viewing on TECH PREVIEW.