Will Xilinx Open the FPGA ASIC Market?

The very nature of FPGAs was designed to handle a wide range of applications. In other words, rather than focusing on a specific application, they were created to allow engineers to design all the applications they develop in the easiest and most convenient way. Compared to ASICs or ASSPs, which are built to focus on specific applications, FPGAs can be considered significantly open ICs. However, FPGAs also have disadvantages; specifically, while there are fewer quantity constraints compared to ASICs, they are more expensive. Furthermore, because they must consider many applications, they are naturally larger in size and consume significantly more power than conventional ASICs.

From the perspective of FPGA companies, the ASIC market, where profitability depends on mass-producing and supplying a single unit designed for a specific application, is undeniably an attractive field that they would love to enter.

It seems that Xilinx’s ambitiously announced Virtex 7 series was also intended to bring them one step closer to that goal. In particular, TSMC’s High K metal gate process, which can achieve over 50% reduction in power consumption, appears to be a green light for targeting the portable handheld market via charging.

ARTIX 7, KINTEX 7, Virtex 7

Virtex is a familiar name as it has been released as a series by Xilinx, but ARTIX 7 and KINTEX 7 are somewhat unfamiliar names. Vincent Tong, Senior Vice President at Xilinx, stated that while the 50% reduction in power consumption is important for this series, it is based on a single integrated architecture that can cover product lines ranging from low-end to high-end. He added that it offers excellent interoperability, particularly in communication and connectivity between main applications requiring high-end devices and sub-applications requiring relatively mid- or low-end devices.

In addition, since this series is manufactured using the 28nm process for the first time, it is estimated that the functional improvement is more than double compared to existing products made using the basic 40nm process, and therefore, it is said that the price can be reduced by 50% compared to existing products relative to functionality.

If you look at the features mainly targeted
1. 2x Improved System Performance
2. Price structure with twice the performance
3. 2.5 times higher capacity
4. It is expected to save twice as much electricity.

In addition, by lowering power in this way, Xilinx can provide a family of FPGAs that support 2.37 TMAC in DSP performance and increase performance to up to 2 million logic cells running at up to 600 MHz and 1.9 Tbps high-speed connectivity, which is significant in that it eliminates the need for designers to struggle with trade-offs between performance and power through FPGAs.

Of course, it is true that a 50% power efficiency was achieved due to the high-K metal gate process, but the technical checkpoints for making it are extremely meticulous.
Basically, careful transistor selection to achieve power reduction goals across all hard blocks, a customer-selectable I/O mode to save additional power while I/O is idle, and a low-power I/O mode that enables high system bandwidth levels with low power consumption have been added.

In addition, for customers requiring further power savings, the ISE Design Suite software release supports the new 28nm FPGA family through 5th generation partial reconfiguration and intelligent clock-gating technologies, which reduce dynamic power by up to 30%. Furthermore, lower power-rated device options with 0.9V Vcc provide an additional 27% reduction in static power and 20% in dynamic power.

Introduction to the Newly Announced Xilinx 7 Series FPGA Family

Virtex-7 Family: The ultra-high-end Virtex-7 family sets a new benchmark in the industry by delivering 2x system performance with 50% lower power consumption compared to Virtex-6 devices, featuring 1.8x improved signal processing performance, 1.5x increased I/O bandwidth, and 2x improved memory bandwidth with 2133 MB/s memory interfacing performance. Additionally, EasyPass-7 devices can be used with any Virtex-7 FPGA without design conversion, guaranteeing a 35% cost reduction. Virtex-7 devices enable the implementation of 400G bridging and switch architecture wired communication equipment—the core of global wired infrastructure, enhanced RADAR systems, and high-performance computer systems—that require single-chip TeraMACC signal processing capabilities, as well as the logic density, performance, and I/O bandwidth required for next-generation test and measurement equipment. The Virtex-7 family includes devices providing up to 1.9 Tbps serial bandwidth and “XT” expansion devices equipped with 80 transceivers operating up to 13.1 Gbps. In addition, these devices provide up to 850 SelectIO pins capable of parallel banks for the industry's largest 72-bit DDR3 memory interface supporting 2133 Mbps. Future devices are also expected to support 28 Gbps transceivers.

Kintex-7 Family: Forming a new FPGA category, the Kintex-7 family delivers the performance of the Virtex-6 family at less than half the price, while doubling the price-performance ratio with 50% lower power consumption. This family provides high-performance 10.3Gbps or optimized low-cost 6.5Gbps serial connectivity, memory, and logic performance required for applications such as high-capacity 10G wired optical communication equipment. In addition, this product family provides a balance of signal processing performance, power consumption, and price for LTE wireless networks