Silicon Labs Launches Industry-Leading 4-PLL Clock IC to Solve Optical Networking Problems

Si537x Timing IC, for OTN Multiservice Platform
Provides highest performance and density, and lowest jitter performance

Silicon Laboratories Inc. (NASDAQ: SLAB, Country Manager Jong-Chan Lee), a global leader in high-performance analog-intensive mixed-signal ICs, announced today the launch of industry-leading performance and highest integration clock IC products designed to address the complex timing requirements of high-speed optical transport network (OTN) applications. Utilizing Silicon Labs' patented DSPLL® technology, the Si5374 and Si5375 clocks are the first single-chip timing ICs to integrate four independent, high-performance phase-locked loops (PLLs), offering twice the PLL integration and 40% lower jitter performance compared to competitors.

OTN is a next-generation protocol (ITU G.8251 and G.709) effective for optical network multiplex services and is an ideal solution for edge routers, wavelength division multiplexing (WDM) transport equipment, Carrier Ethernet, and multiservice platforms. OTN applications require multiple low-jitter clocks at non-integer-related frequencies, leading to complex timing issues. Silicon Labs' Quad-DSPLL Si537x device generates up to eight low-jitter output clocks, simplifying the design of 10G, 40G, and 100G OTN line cards for any protocol or port.

Each DSPLL clock multiplier can be configured to generate frequencies from 2kHz to 808MHz from an input of 2kHz to 710MHz. This excellent frequency flexibility reduces the cost and complexity of multiprotocol OTN line cards by minimizing the need for multiple jitter-cleaning clock ICs. The flexible DSPLL architecture of the Si537x devices achieves industry-leading jitter performance of 0.4 ps (picoseconds). This allows for the simple generation of a high-speed PHY reference clock, eliminating the need for the separate VCXO-based PLLs used in OTU3 and OTU4.

The Si537x devices can reliably lock gapped clock inputs (critical for OTN line card clock requirements) without a separate upstream low-bandwidth PLL. Other carrier-grade features include SONET-compatible jitter peaks (up to 0.1 dB) and innovative heatless switching capabilities that minimize output clock phase transients during reference switching, generating 25 times less phase transient than competing solutions. Each DSPLL engine features a fully integrated loop filter with a user-programmable bandwidth as low as 4 Hz, enabling wander filtering as well as jitter attenuation configurable on a per-channel basis.

Mike Petrowski, General Manager of Timing Products at Silicon Labs, stated, “Currently in the industry, higher levels of clock integration and very low jitter are needed to minimize design costs and complexity as high-bandwidth data and video/audio services over OTN convergence, as well as increased optical line card port density, are required.”