– NXP Semiconductors NV today announced the LPC4000 family, the world's first asymmetric dual-core digital signal controller architecture based on ARM® Cortex™-M4 and Cortex-M0. The LPC4000 offers the advantage of enabling the development of DSP and MCU applications within a single architecture and development environment. With its dual-core architecture and a suite of configurable peripherals, the LPC4000 enables customers to develop a wide range of applications, including motor control, power management, industrial automation, robotics, medical, automotive accessories, and embedded audio. NXP plans to showcase the LPC4000 simultaneously at Electronica 2010, held in Munich, Germany, from November 9 to 12, and at ARM TechCon, held in Santa Clara, California, from November 9 to 11.

Geoff Lees, Vice President and General Manager of the Microcontroller Product Line at NXP Semiconductors, said, “The LPC4000 means more than just the launch of another Cortex-M4 product.” He explained, “Introducing multi-core processing to microcontroller and DSP applications is important,” adding that “configurable peripherals that reduce LPC4000 users’ reliance on external ASIC functions are equally important.”

Microcontroller designers seeking more efficient computationally intensive algorithm processing methods, and DSP designers who have experienced inconvenience with peripheral usage, will benefit greatly from the unique architecture of the LPC4000 family. The LPC4000 is also an excellent choice for designers looking to upgrade from existing DSC processors.

The NXP LPC4000 product family includes the following components.

• Cortex-M4 Processor. The Cortex-M4 processor combines the advantages of microcontrollers, such as integrated interrupt control, low-power mode, low-cost debugging, and ease of use, with high-performance digital signal processing capabilities, including single-cycle MAC, SIMD (Single Instruction Multiple Data) technology, saturated arithmetic instructions, and floating-point units.
• Optimized Memory Architecture. The LPC4000 features an optimized 256-bit wide flash memory architecture that maximizes Cortex-M4 processor performance while reducing power consumption with minimal memory fetching. The LPC4000 utilizes a dual-bank architecture that provides up to 1MB of flash, enabling secure reprogramming and flexible memory partitioning. The LPC4000 offers 264KB of SRAM, which is the largest capacity among all Cortex-M microcontrollers.
• Cortex-M0 Co-processor. The Cortex-M0 subsystem processor significantly relieves data movement and I/O processing duties that can burden the Cortex-M4 core bandwidth. As a result, the Cortex-M4 can focus entirely on the computational tasks of digital signal control applications. With the application of asymmetric dual cores, developers can reduce the power, cost, and system complexity of single-chip solutions, and make software partitioning much easier.
• Configurable Special Peripherals. The LPC4000 incorporates NXP’s configurable special peripherals, including the State Configurable Timer (SCT), SPI Flash Interface, and Serial GPIO Interface. The SCT subsystem consists of a timer array with a state machine that implements complex functions, including event-controlled PWM waveform generation, ADC synchronization, and dead-time control. The SPI Flash Interface provides complete high-speed memory-mapped connectivity to virtually all SPI and quad-SPI manufacturers. With NXP’s Serial GPIO, introduced for the first time in the LPC4000, developers can work flexibly, such as interfacing with any non-standard serial interface or mimicking various standard serial interfaces (I2S, TDM for multi-channel audio, I2C, etc.). Some products in the LPC4000 family include two HS USB controllers, an on-chip HS PHY, and hardware support