With the release of ISE Design Suite 12.3, IP support for the AXI4 interface for plug-and-play FPGA designs begins.

– With the release of ISE® Design Suite 12.3, Xilinx, as a leader in the FPGA industry, also announced an Intellectual Property (IP) core. This core meets the AMBA® 4 AXI4 standard for connecting functional blocks in System-on-Chip (SoC) designs and supports PlanAhead™ design and analysis tools to improve productivity, as well as intelligent clock gating to reduce dynamic power consumption in Spartan®-6 FPGA designs.

Vin Ratford, Senior Vice President of Global Marketing, stated, “Xilinx is the first company to standardize on the AMBA 4 specification as part of its interconnect strategy to support plug-and-play FPGA designs. For SoC designers making significant investments in AMBA AXI3 and AXI4 interface IP, the reasons to use Xilinx’s programmable platform compared to other FPGA and ASIC solutions are clear.” He added, “The unique flexibility of the AXI4 interconnect not only allows for customization in performance and domains but also enables customers to more easily integrate IP from different domains and different IP providers. It also allows ASIC designers to migrate existing designs and IP to Xilinx FPGAs.”

Xilinx’s selection of the AMBA 4 AXI4 standard means that customers have a consistent way to interconnect IP blocks, enabling better utilization of design resources through IP usage and reuse, and making integration between IP vendors much easier. All of this is made possible by support for plug-and-play FPGA designs. In terms of core accessibility and their assembly tools, ISE Design Suite 12.3 includes Xilinx Platform Studio and System Generator tools that enable designers to quickly configure system architecture, buses, and peripherals, along with an enhanced Core Generator™ tool that reduces design time by increasing accessibility to highly parameterized IP.

Michael Dimelow, Marketing Director for ARM Processors, said, “The increased complexity and scale in new designs mean that communication and interconnects are critical factors for system performance. The openness of the AMBA standard is a tremendous advantage for system designers in that it can expand the types of IP available for SoC and FPGA implementations, thereby accelerating time-to-market.”

Charlie Frazer, Silicon IP Engineering Director at Mercury Computer Systems, said, “We decided to adopt AXI4 for reasons including broad ecosystem support, shortened time-to-market, and alignment with the Xilinx product roadmap, in accordance with Mercury’s contributions to standards and industry influence.”

Xilinx’s adoption of the AMBA protocol not only provides designers with access to established ASIC verification methods and existing AMBA protocol-based IP, but also enables them to easily convert to FPGAs as a carefully selected SoC platform.

Michal Siwiński, Director of Product Management for System and SoC Implementation at Cadence, stated, “Cadence has long provided industry-leading AMBA verification solutions for SoC implementation, and the news of our partnership with Xilinx to support AXI4 will be welcome to SoC designers looking to prototype or produce FPGAs as design targets, trusting in Cadence’s proven advanced IP and comprehensive verification technology.” He added, “Xil“The collaboration between Lynx and Cadence means that integrators can more easily model and verify their designs using bus functional models in any tool suite,” he said.

Expansion of PlanAhead RTL Design, Development, and Cockpit Analysis
The PlanAhead design tool in the ISE Design Suite software provides a seamless “push-button” flow as well as advanced visualization and analysis flows. The PlanAhead tool cockpit also includes project management, synthesis, core generator integration, floorplanning, place-and-route, ChipScope Pro tool integration, and bitstream generation. Direct access and searching of the entire Xilinx IP catalog, including AXI4 protocol IP cores, is possible from the same design cockpit.

Intelligent clock gating support for Spartan-6 FPGA
First released in May 2010, ISE Design Suite 12 introduced intelligent clock-gating technology for the first time in the FPGA industry, along with fully automated analysis capabilities and fine-grain (logic slice) optimization features to reduce the number of transitions, which are considered the most critical factor in dynamic power consumption in digital design.