60MHz transmission bandwidth can be linearized using DPD

October 27, 2011 – Linear Technology Korea (General Manager Hong Sa-kwak, www.linear.com ) announced the release of a family of dual (LTC2158-14) and single (LTC2153-14) high IF sampling 14-bit 310 Msps analog-to-digital converters (ADCs). These products are specifically designed for wideband digital predistortion (DPD) linearization applications. DPD is a closed-loop feedback system that samples distortion bandwidth at the output of a base station transmitter and modulates the input signal to cancel out intermodulation distortion products from the power amplifier. This allows the transmitter to operate at a 1 dB compression point of maximum efficiency where the power amplifier (PA) response is nonlinear.

Due to performance constraints on conventional ADCs, transmission bandwidth was limited to 20–40 MHz depending on the implementation of IF sampling or I/Q sampling DPD architectures. To linearize a 20 MHz transmission bandwidth, the feedback loop for the linearization algorithm must acquire 5th-order intermodulation products up to 100 MHz (five times the transmission bandwidth), and a 12-bit ADC with a sampling rate of up to 200 Msps for IF sampling (or 100 Msps for I/Q sampling) is required. Meanwhile, as data demand from mobile users increases, next-generation base stations are being configured to achieve high transmission bandwidths of up to 60 MHz. Linearizing a 60 MHz transmission bandwidth requires an ADC with a minimum resolution of 14 bits and an I/Q sampling architecture with a minimum sampling rate of 300 Msps. In addition, the closed-loop DPD algorithm requires short latency in the feedback path to achieve higher efficiency in PA.
The LTC2158-14 is the industry's first dual 310 Msps ADC that enables transmission bandwidth linearization of up to 60 MHz using I/Q sampling and provides short pipeline transmission latency with only 5 clock cycles for fast adaptation. The single version, the LTC2153-14, is ideal for IF sampling architectures with a transmission bandwidth of up to 30 MHz.

The dual LTC2158-14, operating on a single 1.8V supply, consumes 362mW per channel at a speed of 310Msps and provides a signal-to-noise ratio (SNR) of 68.8dB and an SFDR of 88dB in the baseband with an easy-to-drive 1.32Vp-p input range. The LTC2158 and LTC2153 are part of a pin-compatible 170Msps to 310Msps dual and single ADC family available in 14-bit and 12-bit resolutions. Based on features such as a full analog power bandwidth of 1.25GHz and ultra-low jitter of 0.15psRMS, these products enable undersampling of the IF frequency along with excellent noise performance. These ADCs offer double data rate (DDR) LVDS digital outputs, as well as programmable LVDS output current and 100Ω termination options.

Available in compact 9mm x 9mm (dual) and 6mm x 6mm (single) QFN packages, these new ADC products can also be ordered with commercial or industrial temperature ratings. Demo boards and samples are available through each branch office. The 14-bit dual 310Msps LTC2158-14 is priced at $168.30 per unit in 1,000-unit quantities. For information on the full product family, see www.linear.com/hsadc .

Photo caption: LTC2158-14 I/Q DPD Receiver

Product Features: LTC2153/LTC2158

• 14-bit/12-bit, 310Msps Single/Dual ADC
• 68.8dB SNR, 88dB SFDR (14-bit)
• 724mW (362mW per channel)
• 1.8V single supply operation
• DDR LVDS output
• Easy-to-drive 1.32Vp-p input range
• 1.25GHz Full Power Bandwidth S/H
• Clock duty cycle stabilizer option available
• Low-power sleep and nap modes
• Serial SPI port for configuration
Easily evaluated using PScope™ analysis software