With Xilinx ISE Design Suite 13.3 fully customizable precision floating-point support
Improving DSP Designer Productivity

Available in system generators for DSPs
Single, double, and fully custom precision floating-point numbers with accurate new bits and cycles

Xilinx Korea (Country Manager Heung-Sik Ahn) November 4, 2011 – Xilinx announced ISE® Design Suite 13.3, featuring new capabilities that enable DSP designers to easily execute bit-accurate single, duplex, and fully custom high-precision floating-point mathematical operations in designs targeting wireless, medical, aerospace, defense, high-performance computing, and video applications. This computational workflow is made possible through System Generators for DSPs and utilizes Xilinx’s floating-point operator IP, LogiCORE™. The combination of System Generators for DSPs’ award-winning productivity and single, duplex, and the industry's only fully custom precision floating-point capabilities provides DSP designers with a powerful environment to easily generate, simulate, and execute floating-point designs, as well as more flexible control over the silicon area and power requirements of the system.

Tom Feist, Senior Marketing Director of Design Methodology Marketing at Xilinx, stated, “As the only system generator for DSPs compared to competitor solutions, it provides developers with a solution of exact bits, ensuring that simulation models match hardware execution.” He added, “The Xilinx 7 Series 28nm FPGA delivers up to 1.33 teraflops of single-precision floating-point performance in a single device, enabling it to address the demand for an easy-to-use design flow that delivers sophisticated results.”

Xilinx floating-point arithmetic cores enable a defined range of floating-point arithmetic operations that can be executed on FPGAs. These operations are specified when the core is generated via the Core Generator tool and the current System Generator, and each operation variable commonly features an AXI-4 streaming interface. Previously, it was possible to design floating-point operations on Xilinx FPGAs using fully custom high-precision floating-point IP available in the Core Generator. However, the design flow required an understanding of VHDL or Verilog, and simulation was very challenging for DSP developers. With the release of ISE Design Suite 13.3, designers can implement systems from higher-level concepts and leverage the simulation capabilities of MathWorks’ Simulink® tool to ensure that designs reliably meet accuracy requirements.

ISE Design Suite 13.3 adds Red Hat Enterprise Linux 6 and supports productivity enhancements for users of the Logic, Embedded, and System editions. All versions include plug-and-play IP for Series 7 devices and improvements to device support. The Embedded and System editions include easy-to-use and critical Platform Studio improvements, including a new graphical design view. The Logic edition includes productivity improvements for the PlanAhead™ design analysis tool, including a graphical layer viewer for HDL files.

Customers can download ISE Design Suite 13.3 and get started now. For more detailed information on floating-point numbers, check YouTube or download Xilinx’s latest white paper on floating-point support in system generators (Floating-point DSP Algorithms) to see how IDS 13.3 can improve productivity.

Supply timing
ISE Design Suite 13 is available outright for all ISE editions, starting at $2,995 for the Logic Edition, and supports 32-bit and 64-bit Windows 7. All features are available for free via a 30-day trial on the Xilinx website. (For more information on the release of ISE Design Suite 13 software or on the power and cost-saving design methods and productivity innovations introduced in ISE Design Suite 13, please visit www.xilinx.com/ISE)