Altera Announces OpenCL Program for FPGA Use, Industry First

Completed initial customer evaluation for FPGA-based OpenCL implementation

Hong Kong, November 16, 2011 — Altera (NASDAQ: ALTR) announced that it provides a development program supporting the Open Computing Language (OpenCL™) standard for use with FPGA and SoC FPGA. The OpenCL standard is an open C-based standard enabling parallel programming. Altera's OpenCL program combines FPGA's parallel performance with the OpenCL standard, enabling powerful system acceleration. This heterogeneous system (CPU plus FPGA using OpenCL standard) also enables significant reduction in time-to-market compared to conventional FPGA development using lower-level HDL (hardware description language) such as Verilog or VHDL. Through its OpenCL program, Altera is establishing collaborative relationships with diverse customers, expanding its university program to support the OpenCL standard when developing FPGA at universities, and making active efforts to further advance the OpenCL standard by reflecting customer feedback. Looking at results from early adopters of this program, performance can be improved up to 35 times compared to multi-core CPU solutions, and development time can be reduced by up to 50 percent compared to HDL-developed FPGA solutions.

The OpenCL standard, developed by an industry consortium called the Khronos Group, is a royalty-free open standard that enables cross-platform parallel programming of heterogeneous systems. As a standard parallel language, OpenCL enables programmers to develop code using familiar C-based language across multiple platforms ranging from CPU to GPU, and now this platform has been extended to FPGA as well.

By adopting OpenCL's heterogeneous architecture, system designers can not only maximize the performance of algorithm-intensive portions in their designs but also reduce time-to-market. Suitable applications can range from high-performance computing such as climate and financial modeling to advanced radar systems, medical imaging, video encoding and processing, and any system requiring high-speed computation that can be parallelized is appropriate for this use.

Udi Landen, Vice President of Software and IP Engineering at Altera, said, "The OpenCL standard allows designers to accelerate their designs and improve productivity by leveraging parallel architectures within a C programming environment. Our company has actively participated in efforts to advance the OpenCL standard over the years and is collaborating with industry consortiums, customers, and universities to enhance FPGA support with the OpenCL standard."

The OpenCL standard naturally separates "host" code (pure software written in standard C/C++ that can run on any type of microprocessor) and "kernel" code (written in OpenCL C and executed on an accelerator). System designers can profile their algorithms and select which functions to accelerate as kernels on FPGA devices to improve system performance. Processing can be further accelerated by executing multiple kernels in parallel. The host communicates with the accelerator device through a series of library routines, and with minimal extension capabilities, programmers can specify parallelization and memory hierarchy for the most computation-intensive portions in their code.

At www.altera.com/OpenCL, more detailed information on Altera's OpenCL program can be found, including white papers, online training, and update registration. For detailed information on the OpenCL standard, please visit www.khronos.org/opencl.